Semiconductor device with vertically integrated pHEMTs

Patent metadata

Field	Value
Publication number	US-9923088-B2
Application number	US-201615239005-A
Country	US
Kind code	B2
Filing date	Aug 17, 2016
Priority date	Jul 8, 2016
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

The present disclosure relates to a semiconductor device with vertically integrated pseudomorphic high electron mobility transistors (pHEMTs). The disclosed semiconductor device includes a substrate, a lower pHEMT structure with a lower pHEMT, an isolation layer, and an upper pHEMT structure with an upper pHEMT. The lower pHEMT structure is formed over the substrate and has a first region and a second region that is laterally disposed with the first region. The lower pHEMT is formed in or on the second region. The isolation layer resides over the first region. The upper pHEMT structure is formed over the isolation layer and does not extend over the second region. Herein, the isolation layer separates the lower pHEMT structure from the upper pHEMT structure such that the lower pHEMT and the upper pHEMT operate independently from each other.

First claim

What is claimed is:

1. An apparatus comprising:
a substrate;
a lower pseudomorphic high electron mobility transistor (pHEMT) structure formed over the substrate and having a first region and a second region that is laterally disposed with the first region, wherein:
the lower pHEMT structure comprises a lower doping layer doped with at least one n-type dopant; and
a lower pHEMT is formed in or on the second region;

an isolation layer residing over the first region; and
an upper pHEMT structure formed over the isolation layer and not extending over the second region, wherein:
the upper pHEMT structure comprises an upper doping layer doped with at least one n-type dopant;
an upper pHEMT is formed in or on the upper pHEMT structure; and
the isolation layer separates the lower pHEMT structure from the upper pHEMT structure such that the lower pHEMT and the upper pHEMT operate independently from each other.

2. The apparatus of claim 1 wherein the isolation layer does not extend over the second region.

3. The apparatus of claim 1 wherein the isolation layer is formed of aluminum gallium arsenide (Al x Ga 1−x As), wherein x has a value between 0 and 1 representing relative quantities of respective elements.

4. The apparatus of claim 1 wherein the isolation layer is formed of Indium gallium phosphide (In y Ga 1−y P), wherein y has a value between 0.4 and 0.6 representing relative quantities of respective elements.

5. The apparatus of claim 1 wherein the isolation layer is formed of aluminum indium gallium phosphide (Al x In y Ga 1−y−x P), wherein:
x, y, and 1−x−y represent relative quantities of respective elements; and
x has a value between 0 and 1, y has a value between 0.4 and 0.6, and 1−x−y has a non-negative value.

6. The apparatus of claim 1 wherein the isolation layer is doped with at least one p-type dopant at a doping concentration between 1E17/cm 3 and 1E20/cm 3 .

7. The apparatus of claim 6 wherein at least one p-type dopant comprises one of a group consisting of carbon(C), zinc (Zn), magnesium (Mg), and beryllium (Be).

8. The apparatus of claim 1 wherein the isolation layer has a thickness between 50 Å and 5000 Å.

9. The apparatus of claim 1 wherein the upper pHEMT is one of a depletion mode transistor and an enhancement mode transistor, and the lower pHEMT is one of the depletion mode transistor and the enhancement mode transistor.

10. The apparatus of claim 9 wherein the lower pHEMT comprises a lower channel layer and the upper pHEMT comprises an upper channel layer, wherein the lower channel layer is formed from a different layer other than the upper channel layer, and the lower channel layer is independent from the upper channel layer.

11. The apparatus of claim 10 wherein the lower pHEMT further comprises a lower Schottky layer and the upper pHEMT further comprises an upper Schottky layer, wherein the lower Schottky layer is formed from a different layer other than the upper Schottky layer, and the lower Schottky layer is independent from the upper Schottky layer.

12. The apparatus of claim 1 wherein the lower pHEMT comprises a lower channel layer and the upper pHEMT comprises an upper channel layer, wherein the lower channel layer is formed from a different layer other than the upper channel layer, and the lower channel layer is independent from the upper channel layer.

13. The apparatus of claim 12 wherein the lower pHEMT further comprises a lower Schottky layer and the upper pHEMT further comprises an upper Schottky layer, wherein the lower Schottky layer is formed from a different layer other than the upper Schottky layer, and the lower Schottky layer is independent from the upper Schottky layer.

14. The apparatus of claim 12 wherein the lower channel layer extends through both the first region and the second region.

15. The apparatus of claim 12 wherein the lower pHEMT further comprises a lower cap layer, which is formed at a top portion of the lower pHEMT structure and below the isolation layer, wherein the isolation layer and the lower cap layer are used to optimize a capacitance generated between the lower channel layer and the upper channel layer.

16. The apparatus of claim 12 wherein the lower channel layer and the upper channel layer are formed from undoped indium gallium arsenide (InGaAs).

17. The apparatus of claim 1 wherein the lower pHEMT comprises a lower Schottky layer and the upper pHEMT further comprises an upper Schottky layer, wherein the lower Schottky layer is formed from a different layer other than the upper Schottky layer, and the lower Schottky layer is independent from the upper Schottky layer.

18. The apparatus of claim 17 wherein the lower Schottky layer extends through both the first region and the second region.

19. The apparatus of claim 18 wherein the lower Schottky layer comprises at least one of a group consisting of gallium arsenide (GaAs), AlGaAs, InGaP, aluminum indium phosphide (AlInP), aluminum indium gallium phosphide (AlInGaP), and aluminum gallium (AlAs), and the upper Schottky layer comprises at least one of a group consisting of GaAs, AlGaAs, InGaP, AlInP, AlInGaP, and AlAs.

20. The apparatus of claim 18 wherein the lower Schottky layer comprises AlGaAs, wherein a percentage of aluminum in the AlGaAs is between 18% and 26%.

21. The apparatus of claim 18 wherein the upper Schottky layer comprises AlGaAs, wherein a percentage of aluminum in the AlGaAs is between 18% and 26%.

22. The apparatus of claim 1 wherein the lower pHEMT structure comprises a lower buffer layer, which is formed over the substrate and at a bottom portion of the lower pHEMT structure, and the upper pHEMT structure comprises an upper buffer layer, which is formed over the isolation layer and at a bottom portion of the upper pHEMT structure.

23. The apparatus of claim 22 wherein the lower buffer layer is formed of at least one of undoped gallium arsenide (GaAs) and undoped AlGaAs, and the upper buffer layer is formed of at least one of undoped gallium arsenide (GaAs) and undoped AlGaAs.

24. The apparatus of claim 1 further comprising an isolation implant that extends through the lower pHEMT structure and extends into the substrate such that the isolation implant separates the first region and the second region.

25. The apparatus of claim 24 wherein the isolation implant is formed from aluminum (Al) or helium (He) ions at a dose between 1E12/cm 2 and 5E13/cm 2 .

26. The apparatus of claim 1 wherein the isolation layer is doped with C at a doping concentration between 1E17/cm 3 and 1E20/cm 3 .

27. The apparatus of claim 26 wherein the isolation layer is directly between an undoped buffer layer of the upper pHEMT structure and a doped cap layer of the lower pHEMT structure.

28. The apparatus of claim 1 wherein the lower doping layer of the lower pHEMT structure is a lower delta doping layer, and the upper doping layer of the upper pHEMT structure is an upper delta doping layer.

Assignees

• Qorvo Us Inc

Inventors

• Nevers Corey A
• Hurtt Sheila K
• Schwartz Dana A

Classifications

• H01L29/7786 Primary

  Electricity · mapped topic

• H01L29/0619

  Electricity · mapped topic

• H01L27/095

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H10D84/86 Primary

  of Schottky-barrier gate FETs · CPC title