Trench silicide contact with low interface resistance

Patent metadata

Field	Value
Publication number	US-8927378-B2
Application number	US-201313772954-A
Country	US
Kind code	B2
Filing date	Feb 21, 2013
Priority date	Nov 11, 2010
Publication date	Jan 6, 2015
Grant date	Jan 6, 2015

Abstract

An electrical structure is provided that includes a dielectric layer present on a semiconductor substrate and a via opening present through the dielectric layer.
An interconnect is present within the via opening. A metal semiconductor alloy contact is present in the semiconductor substrate. The metal semiconductor alloy contact has a perimeter defined by a convex curvature relative to a centerline of the via opening. The endpoints for the convex curvature that defines the metal semiconductor alloy contact are aligned to an interface between a sidewall of the via opening, a sidewall of the interconnect and an upper surface of the semiconductor substrate.

First claim

What is claimed is:

1. A method of forming a semiconductor device comprising:
forming a gate structure on a channel portion of a semiconductor substrate, wherein a source region and a drain region are present on opposing sides of the channel portion of the semiconductor substrate;
forming a dielectric layer over the gate structure;
forming a via opening through the dielectric layer to an exposed surface of the semiconductor substrate containing at least one of the source regio…

Assignees

• IBM

Inventors

• Pei Chengwen
• Johnson Jeffrey B
• Li Zhengwen
• Yu Jian

Classifications

• H10P30/222 Primary

  Electricity · mapped topic

• H10D64/0112

  Electricity · mapped topic

• H10W20/083

  Electricity · mapped topic

• H10W20/40

  Electricity · mapped topic

• H10W20/057 Primary

  Electricity · mapped topic