Semiconductor memory device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-9922991-B2
Application number	US-201615267623-A
Country	US
Kind code	B2
Filing date	Sep 16, 2016
Priority date	Mar 16, 2016
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A semiconductor memory device includes a stacked body including a first electrode layer and a second electrode layer stacked on the first electrode layer, and first and second interconnections on a first surface of the stacked body. The first and second electrode layers have first and second end surfaces respectively in the first surface. The first interconnection is electrically connected to the first electrode layer through a first region of the first end surface; and the second interconnection is electrically connected to the second electrode layer through a second region of the second end surface. The first and second interconnections extend in a first direction on the first surface. The first and second regions are arranged in a second direction crossing the first direction with a crossing angle smaller than 90 degrees. The first region and the second region each have a boundary along the second direction.

First claim

What is claimed is:

1. A semiconductor memory device, the device comprising:
a stacked body including a first electrode layer and a second electrode layer stacked on the first electrode layer, the stacked body having a first surface crossing a stacked direction toward the second electrode layer from the first electrode layer, wherein the first electrode layer having a first end surface in the first surface, and the second electrode layer having a second end surface in the first surface;
a semiconductor layer extending through the stacked body in the stacked direction;
a first interconnection electrically connected to the first electrode layer through a first region provided in the first end surface; and
a second interconnection electrically connected to the second electrode layer through a second region provided in the second end surface,
the first and second interconnections extending in a first direction on the first surface; the first region and the second region being arranged in a second direction crossing the first direction with a crossing angle smaller than 90 degrees; and the first region and the second region each having a boundary along the second direction.

2. The device according to claim 1 , wherein the first electrode layer and the second electrode layer have an end portion inclined with respect to the stacked direction.

3. The device according to claim 1 , wherein the first end surface and the second end surface extend in a third direction crossing the first direction and the second direction in the first surface.

4. The device according to claim 3 , wherein each of the first region and the second region further has a boundary along the third direction.

5. The device according to claim 1 , further comprising:
a first insulating layer provided on the stacked body,
wherein the first region and the second region are a part of the first end surface and a part of the second end surface exposed at a bottom surface of a groove provided in the first insulating layer and extending in the second direction.

6. The device according to claim 1 , further comprising:
a first conductive body provided on the first region; and
a second conductive body provided on the second region,
wherein the first interconnection is electrically connected to the first electrode layer through the first conductive body, and
the second interconnection is electrically connected to the second electrode layer through the second conductive body.

7. The device according to claim 1 , further comprising:
an underlying layer adjacent to the first electrode layer on a side of the stacked body opposite to the first surface; and
a support body provided on the underlying layer, a part of the support body being positioned between the underlying layer and an end portion of the first electrode layer,
wherein the support body has a sidewall inclined with respect to the stacked direction, and
the end portion of the first electrode layer extends along the sidewall.

8. The device according to claim 7 , wherein
the support body has a first surface on a side opposite to the underlying layer, and
the first surface of the stacked body is positioned at a same level as the first surface of the support body.

9. The device according to claim 7 , wherein the first interconnection and the second interconnection extend in the first direction on the support body.

10. The device according to claim 1 , further comprising:
a first insulating body extending in the stacked direction through the stacked body.

11. The device according to claim 1 , wherein the first region and the second region each have a parallelogram like shape.

12. The device according to claim 1 , further comprising:
second insulating bodies provided along the second direction on both sides of the first region and the second region.

13. The device according to claim 12 , wherein
no portion of the stacked body lies under the second insulating bodies.

Assignees

• Toshiba Memory Corp

Inventors

• Kamigaki Tetsuya
• Hasegawa Isahiro
• Ito Shinichi
• Inoue Soichi
• Higashiki Tatsuhiko
• Hattori Kei
• Matsuno Koichi
• Morita Seiji

Classifications

• H10P14/46

  using a liquid · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title