Address translation in memory

Patent metadata

Field	Value
Publication number	US-2016147667-A1
Application number	US-201514813111-A
Country	US
Kind code	A1
Filing date	Jul 29, 2015
Priority date	Nov 24, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

According to one general aspect, a computational memory may include memory cells configured to store data and a page table, wherein the page table maps, at least in part, a virtual address to a physical address. The computational memory may also include at least one processor-in-memory. Each processor-in-memory may be configured to: receive a request to execute an instruction utilizing the portion of the data stored by the memory cells, wherein the request includes the virtual address, request the physical address from a translator, and execute the instruction utilizing the physical address. The computational memory may further include the translator which may be configured to, for each processor-in-memory, convert, by accessing the page table, a virtual address associated with a portion of the data to a physical address associated with the portion of the data.

First claim

What is claimed is:

1 . A computational memory comprising:
memory cells configured to store data and a page table, wherein the page table maps, at least in part, a virtual address to a physical address; at least one processor-in-memory each configured to:
receive a request to execute an instruction utilizing the portion of the data stored by the memory cells, wherein the request includes the virtual address,
request the physical address from a translator, and
execute the instruction utilizing the physical address; and
the translator configured to, for each processor-in-memory, convert, by accessing the page table, a virtual address associated with a portion of the data to a physical address associated with the portion of the data.

2 . The computer memory of claim 1 , wherein the translator is configured to:
receive a second translation request originating from a central processor external to the computational memory, wherein the second translation request includes a second virtual address; and convert, by accessing the page table, the second virtual address to a second physical address; and transmit the second physical address to the central processor.

3 . The computational memory of claim 1 , wherein the computational memory comprises an input/output decoder/encoder configured to:
receive a translation request message, wherein the translation request message includes a virtual address, and transmit a translation response message that includes either a physical address that corresponds to the virtual address or an error.

4 . The computational memory of claim 1 , wherein the translator is configured to convert the virtual address to the physical address without the assistance of a component external to the computational memory.

5 . The computational memory of claim 1 , further comprising a page table walker configured to convert the virtual address the data to the physical address;
wherein the page table walker receives the virtual address and a page table pointer; wherein the page table walker is configured to access the page table via the page table pointer, and search for the virtual address in the page table; and wherein the page table walker is configured to, in response, receive either a physical address or a second page table pointer.

6 . The computational memory of claim 5 , further comprising a protection and fault handler configured to determine if the instruction is allowed to access the data stored at the physical address; and
wherein the protection & fault handler is configured to:
receive the physical address and a security identifier associated with instruction,
determine if the physical address is associated with the security identifier, and
if the physical address is not associated with the security identifier, generate a security exception.

7 . The computational memory of claim 5 , further comprising a cache configured to map virtual address to physical addresses; and
wherein the translator is configured to:
determine if the virtual address is stored in the cache,
if not, convert the virtual address to the physical address via the page table walker,
if so, convert the virtual address to the physical address via the cache, and
store a mapping of the virtual address to the physical address in the cache after the translator has converted the virtual address to the physical address.

8 . The computational memory of claim 1 , wherein the translator is configured to return the physical address without determining if the instruction is allowed to access the data stored at the physical address.

9 . The computational memory of claim 1 , wherein the translator is configured to iteratively walk through the page table until the virtual address is found in order to convert the virtual address to the physical address.

10 . The computational memory of claim 1 , further comprising:
a first integrated circuit die that comprises the translator and the processor, and at least a second integrated circuit die that comprises the memory cells; and wherein the first integrated circuit die and the second integrated circuit die are coupled to form a stack of dies.

11 . A method of performing translation-in-memory by a computational memory, the method comprising:
receiving, from a processor, a translation request message, wherein the translation request message includes a virtual address; converting the virtual address to a corresponding physical address by accessing only memory cells included in the computational memory; and transmitting, to the processor, a translation response message that includes either the physical address that corresponds to the virtual address or an error.

12 . The method of claim 11 , wherein receiving comprises receiving a translation request message from a processor-in-memory that is included by the computational memory.

13 . The method of claim 11 , wherein the receiving comprises receiving a translation request message from a memory management unit that is external to the computational memory.

14 . The method of claim 11 , wherein converting comprises:
iteratively walking through page tables stored by the computational memory; and when the virtual address is found in the page tables, retrieving the physical address from the page tables.

15 . The method of claim 11 , further comprising determining if the physical address is associated with a security identifier, wherein the translation request message includes the security identifier; and
wherein transmitting a translation response message comprises:
if the physical address is associated with a security identifier, including the physical address in the translation response message, and
if the physical address is not associated with a security identifier, including the error in the translation response message.

16 . An apparatus comprising:
an input/output decoder/encoder configured to:
receive a translation request message, wherein the translation request message includes a virtual address, and
transmit a translation response message that includes either a physical address that corresponds to the virtual address or an error; and
a translation-in-memory circuit configured to convert the virtual address to the physical address by accessing memory cells included by the apparatus.

17 . The apparatus of claim 16 , further including a protection and fault handler circuit configured to:
receive a security identifier, wherein the translation request message includes the security identifier, receive the physical address, determine if the physical address is associated with the security identifier, and if the physical address is not associated with the security identifier, generate an security exception.

18 . The apparatus of claim 16 , wherein the translation request message includes a page table pointer; and
wherein the translation-in-memory circuit comprises a page table walker configured to:
access, via the page table pointer, a page table stored in the memory cells,
search for the virtual address in the page table, and
receive, from the page table, the physical address.

19 . The apparatus of claim 18 , wherein the translation-in-memory circuit comprises a cache configured to map virtual address to physical addresses; and
wherein the translation-in-memory circuit is configured to:
determine if the virtual address is stored in the cache,
if not, convert the virtual address to the physical address via the page table walker,
if so, convert the virtual add

Assignees

• Samsung Electronics Co Ltd

Inventors

• Awasthi Manu
• Chang Kevin

Classifications

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title

• G06F2212/651

  Multi-level translation tables · CPC title

• G06F2212/657

  Virtual address space management · CPC title

• G06F12/145

  the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism · CPC title

• G06F2212/1052

  Security improvement · CPC title