Direct memory access controller

Patent metadata

Field	Value
Publication number	US-9921985-B2
Application number	US-201514860398-A
Country	US
Kind code	B2
Filing date	Sep 21, 2015
Priority date	Dec 15, 2006
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A system has at least one bus, a central processing unit (CPU) coupled with the bus, a memory coupled with the bus, a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from the CPU and being coupled with the bus, wherein for access to the bus the DMA controller is programmable in a first mode to have priority over the CPU and in a second mode in which at least one DMA channel of the DMA controller is suspended from accessing the bus.

First claim

What is claimed is:

1. A microcontroller comprising:
a bus;
a central processing unit (CPU) coupled with said bus;
a memory coupled with said bus;
a plurality of peripherals coupled with the bus;
a direct memory access (DMA) controller having a plurality of DMA channels and operating independently from said CPU and being coupled with said bus, wherein for access to said bus said DMA controller is programmable in a first mode to have priority over said CPU and the plurality of peripherals and in a second mode to immediately suspend data transfer on all DMA channels and grant the CPU direct access to the bus.

2. The system according to claim 1 , further comprising a control register coupled with said DMA controller and for programming said DMA controller, said control register comprising a bit for setting said first or second mode.

3. The system according to claim 1 , wherein said first or second mode are programmable through a control signal fed to said DMA controller.

4. The system according to claim 1 , wherein each of said plurality of DMA channels has an assigned priority level.

5. The system according to claim 1 , wherein said DMA controller comprises for each channel a channel control register.

6. The system according to claim 5 , wherein each channel control register comprises a programmable bit controlling whether said channel is enabled or disabled.

7. The system according to claim 4 , wherein said first or second mode is programmable through a control signal fed to said DMA controller comprising a priority level.

8. A method for performing a data transmission within a microcontroller according to claim 1 , the method comprising:
programming said DMA controller to operate in the first mode, wherein upon request for a DMA data transmission, granting the DMA controller access to said bus;
thereafter programming said DMA controller to operate in the second mode to immediately suspend data transfer on all DMA channels;
granting the master device access to said bus;
performing at least one bus access by said master device; and
thereafter programming said DMA controller to operate in the first mode to resume data transfer on all DMA channels.

9. The method according to claim 8 , wherein said steps of programming said DMA controller are performed by a configurable register.

10. The method according to claim 9 , wherein said steps of programming said DMA controller are performed by setting and resetting a bit in said configurable register.

11. The method according to claim 8 , wherein said steps of programming said DMA controller are performed by feeding a control signal to said DMA controller.

12. The method according to claim 11 , wherein said control signal is generated from an exception signal fed to the master device.

13. The method according to claim 8 , wherein if a data transfer of said data transfer has been initiated by said DMA controller before suspension has been initiated then finishing said data transfer and then suspending access of said DMA controller.

14. The method according to claim 8 , wherein said master device is a central processing unit (CPU) and said step of programming is performed by said CPU.

15. The method according to claim 8 , wherein said master device is a peripheral device and said step of programming is performed by a central processing unit.

16. The method according to claim 8 , wherein said DMA controller is operable to cycle through multiple DMA channels transactions of DMA channels having the same priority level.

17. A method for performing a data transmission over a bus coupled with a master device and a direct memory access (DMA) controller having a plurality of DMA channels; the method comprising:
providing the master device coupled with the bus, a memory coupled with the bus, a plurality of peripheral devices coupled with the bus and the DMA controller coupled with the bus within a microcontroller;
assigning each of said plurality of DMA channels a priority level;
upon request for a DMA data transmission, granting the DMA controller access to said bus with one of said plurality of DMA channels;
feeding a suspend command having a priority level to said DMA controller;
if said priority level in said suspend command is higher than a priority level of said DMA channel having access to said bus, then
suspending any DMA channel having a lower priority than said priority level in said suspend command from accessing said bus;
if no other DMA channel has access to said bus, then
granting the master device access to said bus;
performing at least one bus access by said master device;
feeding a resume command to said DMA controller to resume said DMA data transmission.

18. The method according to claim 17 , wherein said DMA controller is operable to cycle through multiple DMA channels transactions of DMA channels having the same priority level.

19. The method according to claim 17 , wherein said master device is a central processing unit of the microcontroller.

20. The method according to claim 17 , wherein said steps of programming said DMA controller are performed by setting and resetting a bit in a configurable register of the microcontroller.

Assignees

• Microchip Tech Inc

Inventors

• Triece Joseph W
• Pesavento Rodney J
• Lahti Gregg D
• Dawson Steven

Classifications

• G06F13/1689

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F13/30 Primary

  with priority control · CPC title

• G06F13/285

  Halt processor DMA (G06F13/30 takes precedence) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/34 Primary

  with priority control · CPC title