Component-embedded substrate

Patent metadata

Field	Value
Publication number	US-9918381-B2
Application number	US-201514588614-A
Country	US
Kind code	B2
Filing date	Jan 2, 2015
Priority date	Jul 5, 2012
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A component-embedded substrate includes a substrate portion, an embedded electronic component, and a resin portion. The substrate portion has inner electrodes on an inner principal surface. The embedded electronic component has terminal electrodes and is mounted to the substrate portion via solder fillets adhering to the respective terminal electrodes and the respective inner electrodes. The resin portion is stacked on the substrate portion, with the embedded electronic component embedded therein. The resin portion includes a no-filler-added layer and a filler-added layer. The no-filler-added layer extends from the inner principal surface to a height which allows at least the solder fillets to be covered. The filler-added layer contains an inorganic filler and extends from an interface with the no-filler-added layer to a height which allows at least the embedded electronic component to be covered.

First claim

The invention claimed is:

1. A component-embedded substrate comprising:
a substrate portion having an inner principal surface and inner electrodes on the inner principal surface;
an embedded electronic component having terminal electrodes and mounted to the substrate portion via solder fillets adhering to the respective terminal electrodes and the respective inner electrodes; and
a resin portion stacked on the substrate portion, with the embedded electronic component embedded therein,
wherein the resin portion includes
a no-filler-added layer containing no inorganic filler arranged above an entire extent of the inner principal surface of the substrate portion, and extending from the inner principal surface to a height which allows at least the solder fillets to be covered; and
a filler-added layer containing an inorganic filler and extending from an interface with the no-filler-added layer to a height which allows at least the embedded electronic component to be covered,
wherein the filler-added layer covers an entire portion of a top surface of the embedded electronic component, and the no-filler-added layer does not reach the top surface of the embedded electronic component.

2. The component-embedded substrate according to claim 1 , further comprising:
a second substrate portion disposed opposite the substrate portion with the resin portion interposed therebetween; and
a second embedded electronic component mounted to the second substrate portion while being embedded in the resin portion.

3. The component-embedded substrate according to claim 1 , wherein the substrate portion comprises a printed wiring board, a ceramic board, or a supporting plate.

4. The component-embedded substrate according to claim 1 , wherein the embedded electronic component is a passive component comprises a capacitor, a coil, or a resistance chip or the embedded electronic component is an active component comprising an IC chip.

5. The component-embedded substrate according to claim 1 , wherein the resin portion comprises a thermosetting resin or a photo-curable resin.

6. A component-embedded substrate comprising:
a first substrate portion and a second substrate portion each having an inner principal surface and inner electrodes on the inner principal surface, the first substrate portion and the second substrate portion being disposed such that the inner principal surfaces face each other;
a first embedded electronic component having terminal electrodes and mounted to the first substrate portion via first solder fillets adhering to the respective terminal electrodes and the respective inner electrodes;
a second embedded electronic component having terminal electrodes and mounted to the second substrate portion via second solder fillets adhering to the respective terminal electrodes and the respective inner electrodes; and
a resin portion stacked between the substrate portions, with the first embedded electronic component and the second embedded electronic component embedded therein,
wherein the resin portion includes
a first no-filler-added layer containing no inorganic filler arranged above an entire extent of the inner principal surface of the first substrate portion, and extending from the inner principal surface of the first substrate portion to a height which allows at least the first solder fillets to be covered;
a second no-filler-added layer containing no inorganic filler arranged above an entire extent of the inner principal surface of the second substrate portion, and extending from the inner principal surface of the second substrate portion to a height which allows at least the second solder fillets to be covered; and
a filler-added layer containing an inorganic filler and extending from an interface with the first no-filler-added layer to an interface with the second no-filler-added layer,
wherein the filler-added layer covers an entire portion of a top surface of the embedded electronic component, and the first no-filler-added layer does not reach the top surface of the embedded electronic component.

Assignees

• Murata Manufacturing Co

Inventors

• Noda Satoru

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07251

  characterised by changes in properties of the bump connectors during connecting · CPC title

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W70/685 Primary

  comprising multiple insulating layers · CPC title