Eye width measurement and margining in communication systems

Patent metadata

Field	Value
Publication number	US-9917685-B2
Application number	US-201715614470-A
Country	US
Kind code	B2
Filing date	Jun 5, 2017
Priority date	Mar 15, 2013
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

Generally, this disclosure describes eye width measurement and margining in communication systems. An apparatus may be configured to: decouple a phase detector from a CDR loop filter of a receiver under test in response to synchronizing a margining clock signal to a receiver clock signal; apply a margining input to the loop filter, the margining input configured to shift a frequency of the margining clock signal by a constant amount related to the margining input; compare a first bit stream and a second bit stream and configured to detect an error, the first bit stream related to a transmitted bit stream; and count cycles of the receiver clock signal or the margining clock signal, wherein an eye width associated with the receiver under test is related to the margining input, the frequency of the receiver clock signal and a count of clock cycles when the error is detected.

First claim

What is claimed is:

1. A method for eye measurement comprising:
receiving a recovered clock signal, the recovered clock signal being synchronized with a receiver clock signal;
generating a margining clock signal, wherein the recovered clock signal and the margining clock signal are in phase for at least one clock cycle;
applying a phase difference increment to the margining clock signal for a plurality of clock cycles;
comparing the margining clock signal to the recovered clock signal for each clock cycle;
counting clock cycles at least until an error is detected, the error being detected based upon a result of the comparison; and
determining an eye width of the receiver clock signal based, at least in part, on the counted clock cycles when the error was detected and the phase difference increment.

2. The method of claim 1 , wherein the phase difference increment is determined based, at least in part, on a clock accuracy and the recovered clock signal.

3. The method of claim 2 , wherein the clock accuracy is measured in parts per million (PPM).

4. The method of claim 1 , wherein the eye width is determined in response to the error being detected.

5. The method of claim 4 , wherein the eye width is proportional to a product of the counted clock cycles and the phase difference increment.

6. The method of claim 1 , wherein counting clock cycles at least until an error is detected, the error being detected based upon a result of the comparison comprises:
resetting a clock cycle count when a first error is detected, the first error being detected based upon a result of the comparison;
applying an inverted phase difference increment to the margining clock signal for a second plurality of clock cycles subsequent to the first error being detected; and
counting clock cycles at least until a second error is detected, the second error being detected based upon a result of the comparison; and

wherein the eye width of the receiver clock signal is determined based, at least in part, on the counted clock cycles when the second error was detected and the inverted phase difference increment.

7. An on-die eye measurement system comprising:
clock and data recovery circuitry to generate a recovered clock signal, the recovered clock signal being synchronized with a receiver clock signal;
margining circuitry to:
generate a margining clock signal, the margining clock signal being in phase with the recovered clock signal for at least one clock cycle; and
apply a phase difference increment to the margining clock signal for a plurality of clock cycles; and

comparison circuitry to compare the margining clock signal to the recovered clock signal;
counter circuitry to count a number of clock cycles at least until an error is detected, the error being detected based, at least in part, upon an output of the comparison circuitry; and
eye measurement circuitry to determine an eye width of the receiver clock signal based, at least in part, on the counted clock cycles when the error was detected and the phase difference increment.

8. The on-die eye measurement system of claim 7 , wherein the phase difference increment is determined based, at least in part, on a clock accuracy and the recovered clock signal.

9. The on-die eye measurement system of claim 8 , wherein the clock accuracy is measured in parts per million (PPM).

10. The on-die eye measurement system of claim 7 , wherein the eye measurement circuitry determines the eye width in response to the error being detected.

11. The on-die measurement system of claim 10 , wherein the eye width is proportional to a product of the counted clock cycles and the phase difference increment.

12. The on-die eye measurement system of claim 7 , wherein the counter circuitry is reset when an error is detected.

13. The on-die eye measurement system of claim 7 , wherein, responsive to a first error being detected:
the counter circuitry is reset;
the margining circuitry is to apply an inverted phase difference increment to the margining clock signal for a second plurality of clock cycles; and
the counter circuitry is to count a second number of clock cycles until a second error is detected, the second error being detected based, at least in part, upon an output of the comparison circuitry; and

wherein the eye width measurement circuitry is to determine an eye width of the receiver clock signal based, at least in part, on the counted clock cycles when the second error was detected and the inverted phase difference increment.

14. At least one non-transitory computer-readable storage medium having instructions stored thereon which when executed by a processor result in the following operations for measuring an eye, comprising:
receive a recovered clock signal, the recovered clock signal being synchronized with a receiver clock signal;
generate a margining clock signal, wherein the recovered clock signal and the margining clock signal are in phase for at least one clock cycle;
apply a phase difference increment to the margining clock signal for a plurality of clock cycles;
compare the margining clock signal to the recovered clock signal for each clock cycle;
count clock cycles at least until an error is detected, the error being detected based upon a result of the comparison; and
determine an eye width of the receiver clock signal based, at least in part, on the counted clock cycles when the error was detected and the phase difference increment.

15. The non-transitory computer-readable storage medium of claim 14 , wherein the phase difference increment is determined based, at least in part, on a clock accuracy and the recovered clock signal.

16. The non-transitory computer-readable storage medium of claim 15 , wherein the clock accuracy is measured in parts per million (PPM).

17. The non-transitory computer-readable storage medium of claim 14 , wherein the eye width is determined in response to the error being detected.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the eye width is proportional to a product of the counted clock cycles and the phase difference increment.

19. The non-transitory computer-readable storage medium of claim 1 , wherein the instructions resulting in the operations count clock cycles at least until an error is detected, the error being detected based upon a result of the comparison, when executed by the processor, result in further operations comprising:
reset a clock cycle count when a first error is detected, the first error being detected based upon a result of the comparison;
apply an inverted phase difference increment to the margining clock signal for a second plurality of clock cycles subsequent to the first error being detected; and
count clock cycles at least until a second error is detected, the second error being detected based upon a result of the comparison; and

wherein the eye width of the receiver clock signal is determined based, at least in part, on the counted clock cycles when the second error was detected and the inverted phase difference increment.

20. An eye measurement system comprising:
a means for receiving a recovered clock signal, the recovered clock signal being synchronized with a receiver clock signal;
a means for generating a margining clock signal, wherein the recovered clock signal and the margining clock signal are in phase for at least one clock cycle;
a means for applying a phase difference increment to the margining clock signal for a plurality of clock cycles;
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Assignees

• Intel Corp

Inventors

• Hammad Dima
• Levin Vadim
• Laufer Amir
• Bar-Lev Ron
• Familia Noam
• Levin Itamar

Classifications

• H03L7/0807

  concerning mainly a recovery circuit for the reference signal · CPC title

• H04L7/0062

  detection of error based on data decision error, e.g. Mueller type detection · CPC title

• H04L7/0079 Primary

  Receiver details · CPC title

• H04L7/0016

  correction of synchronization errors · CPC title

• H04L1/24

  Testing correct operation · CPC title