Method for fabricating a semiconductor structure

Patent metadata

Field	Value
Publication number	US-9640394-B2
Application number	US-201514835979-A
Country	US
Kind code	B2
Filing date	Aug 26, 2015
Priority date	Aug 27, 2014
Publication date	May 2, 2017
Grant date	May 2, 2017

Abstract

Method for fabricating a semiconductor structure. The method includes: providing a crystalline silicon substrate; defining an opening in a dielectric layer on the crystalline silicon substrate, the opening having sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate; providing a confinement structure above the dielectric layer, thereby forming a confinement region between the confinement structure and the dielectric layer; and growing a crystalline compound semiconductor material in the confinement region thereby at least partially filling the confinement region. The present invention also provides an improved compound semiconductor structure and a device for fabricating such semiconductor structure.

First claim

What is claimed is:

1. A method for fabricating a semiconductor structure comprising:
providing a crystalline silicon substrate;
defining an opening in a dielectric layer on the crystalline silicon substrate, the opening having sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate;
providing a confinement structure above the dielectric layer, thereby forming a confinement region between the confinement structure and the dielectric layer; and
growing a crystalline compound semiconductor material in the confinement region, thereby at least partially filling the confinement region.

2. The method of claim 1 , wherein the confinement structure comprises a cap confinement portion arranged essentially in parallel to a surface of the dielectric layer at a predetermined distance.

3. The method of claim 2 , wherein forming the confinement structure comprises:
forming a sacrificial layer covering the opening and at least partially covering the dielectric layer;
forming a cap layer on the sacrificial layer for forming the cap confinement portion; and
removing the sacrificial layer for forming the confinement region.

4. The method of claim 3 , wherein the sacrificial layer comprises an amorphous semiconductor material.

5. The method of claim 3 , wherein the confinement structure comprises a dielectric material.

6. The method of any one of claim 3 , wherein the confinement structure comprises an inlet that is arranged at a predetermined lateral distance from the opening for inserting compound semiconductor material into the confinement region.

7. The method of claim 3 , wherein the confinement structure is formed in a spaced relationship with the dielectric layer and the bottom of the opening, thereby forming the confinement region that extends above and laterally from the sidewalls of the opening between the confinement structure and the dielectric layer.

8. The method of claim 2 , wherein the confinement structure comprises a plurality of spacer portions arranged between the dielectric layer and the cap confinement portion.

9. The method of claim 8 , wherein the cap layer is a self-supporting structure resting on the spacer portions.

10. The method of claim 1 , wherein growing the compound semiconductor material comprises:
overgrowing the opening with the compound semiconductor material, thereby forming a crystalline compound semiconductor layer on the dielectric layer extending laterally from the opening, and the crystalline compound semiconductor layer being confined by the cap confinement portion.

11. The method of claim 1 , further comprising: removing at least partially the confinement structure.

12. The method of claim 1 , further comprising: removing at least partially the crystalline compound semiconductor material in the opening.

13. The method of claim 1 , wherein the dielectric layer and/or the confinement structure comprises silicon oxide.

14. The method of claim 1 , wherein the bottom of the opening acts as a growth seed for growing the crystalline compound semiconductor material.

15. The method of claim 1 , wherein the crystalline compound semiconductor material includes a III-V compound semiconductor material, a II-VI compound semiconductor material, and/or a IV-IV compound semiconductor material.

16. The method of claim 1 , further comprising:
processing the crystalline compound semiconductor material for fabricating electronic or optical devices.

17. A device for crystalline compound semiconductor growth comprising:
a substrate comprising crystalline silicon material;
a dielectric layer on the crystalline silicon substrate having an opening, the opening having sidewalls and a bottom wherein the bottom corresponds to a surface of the crystalline silicon substrate, and wherein the bottom acts as a growth seed for a compound semiconductor material; and
a confinement structure in a spaced relationship with the dielectric layer and the bottom of the opening thereby forming a confinement region, wherein the confinement region extends laterally from the sidewalls of the opening between the confinement structure and the dielectric layer.

Assignees

• IBM

Inventors

• Caimi Daniele
• Czornomaz Lukas
• Fompeyrine Jean
• Uccelli Emanuele

Classifications

• H10P50/646

  of Group III-V materials · CPC title

• H10P14/3432

  Tellurides · CPC title

• H10P14/3431

  Selenides · CPC title

• H10P14/3428

  Sulfides · CPC title

• H10P14/3421

  Arsenides · CPC title