Nucleation layer for growth of III-nitride structures

US9917156B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-9917156-B1
Application numberUS-201615256170-A
CountryUS
Kind codeB1
Filing dateSep 2, 2016
Priority dateSep 2, 2016
Publication dateMar 13, 2018
Grant dateMar 13, 2018

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Nucleation layers for growth of III-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate. The nucleation layer can include silicon and deep-level dopants. The semiconductor can include a III-nitride layer formed over the nucleation layer. At least one of the silicon substrate and the nucleation layer can include ionized contaminants. In addition, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor, comprising: a substrate; a nucleation layer over the substrate and having deep-level dopants; and a III-V layer formed over the nucleation layer; wherein: at least one of the substrate and the nucleation layer include ionized contaminants, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants, and a concentration of free holes in the substrate and in the nucleation layer is less than 10 16 cm −3 . 2. The semiconductor of claim 1 , wherein: the substrate comprises a substrate material; and the deep-level dopants comprise a deep-level dopant species having deep-level states being separated from conduction and valence bands of the substrate material by between 0.3 eV and 0.6 eV. 3. The semiconductor of claim 1 , further comprising a heterostructure between the substrate and the nucleation layer. 4. The semiconductor of claim 1 , wherein the deep-level dopant comprises vanadium. 5. The semiconductor of claim 1 , wherein the deep-level dopant comprises iron. 6. The semiconductor of claim 1 , wherein the deep-level dopant comprises sulfur. 7. The semiconductor of claim 1 , wherein the ionized contaminants comprise a Group III species. 8. The semiconductor of claim 1 , wherein the ionized contaminants comprise ionized acceptor contaminants. 9. The semiconductor of claim 1 , wherein the concentration of the deep-level dopants is between 10 15 cm −3 and 10 19 cm −3 . 10. The semiconductor of claim 1 , wherein the concentration of the deep-level dopants is between 10 16 cm −3 and 10 18 cm −3 . 11. The semiconductor of claim 1 , wherein a concentration of free holes in the substrate and in the nucleation layer is less than 10 15 cm −3 . 12. The semiconductor of claim 1 , wherein a thickness of the nucleation layer is between 1 nm and 100 nm. 13. The semiconductor of claim 1 , wherein a thickness of the nucleation layer is between 10 nm and 1 μm. 14. The semiconductor of claim 1 , wherein a thickness of the nucleation layer is between 100 nm and 10 μm. 15. The semiconductor of claim 1 , wherein a first concentration of the deep-level dopants at the surface of the nucleation layer nearest the substrate is higher than a second concentration of the deep-level dopants at the surface nearest the III-V layer. 16. The semiconductor of claim 1 , wherein the substrate material is silicon. 17. The semiconductor of claim 1 , wherein the III-V layer is a III-nitride layer. 18. A method of growing a semiconductor, comprising: growing a nucleation layer over a substrate, the nucleation layer having deep-level dopants; and growing a III-V layer over the nucleation layer; wherein: at least one of the substrate and the nucleation layer include ionized contaminants, a concentration of the deep-level dopants is at least as high as a concentration of the ionized contaminants, and a concentration of free holes in the substrate and in the nucleation layer is less than 10 16 cm −3 . 19. The method of claim 18 , wherein: the substrate comprises a substrate material; and the deep-level dopants comprise a deep-level dopant species having deep-level states being separated from the conduction and valence bands of the substrate material by between 0.3 eV and 0.6 eV. 20. The method of claim 18 , further comprising growing a heterostructure between the substrate and the nucleation layer. 21. The method of claim 18 , wherein the deep-level dopants comprise vanadium. 22. The method of claim 18 , wherein the deep-level dopants comprise iron. 23. The method of claim 18 , wherein the deep-level dopants comprise sulfur. 24. The method of claim 18 , wherein the ionized contaminants comprise a Group III species. 25. The method of claim 18 , wherein the ionized contaminants comprise ionized acceptor contaminants. 26. The method of claim 18 , wherein the concentration of deep-level dopants is between 10 15 cm −3 and 10 19 cm −3 . 27. The method of claim 18 , wherein the concentration of deep-level dopants is between 10 16 cm −3 and 10 18 cm −3 . 28. The method of claim 18 , wherein a concentration of free holes in the substrate and in the nucleation layer is less than 10 15 cm −3 . 29. The method of claim 18 , wherein a thickness of the nucleation layer is between 1 nm and 100 nm. 30. The method of claim 18 , wherein a thickness of the nucleation layer is between 10 nm and 1 μm. 31. The method of claim 18 , wherein a thickness of the nucleation layer is between 100 nm and 10 μm. 32. The method of claim 18 , wherein a first concentration of the deep-level dopants at the surface of the nucleation layer nearest the substrate is higher than a second concentration of the deep-level dopants at the surface nearest the III-V layer. 33. The method of claim 18 , wherein the substrate material is silicon. 34. The method of claim 18 , wherein the III-V layer is a III-nitride layer. 35. The method of claim 18 , comprising growing the nucleation layer and III-V layer by metalorganic chemical vapor deposition. 36. The method of claim 18 , comprising growing the nucleation layer and the III-V layer by molecular beam epitaxy. 37. The method of claim 18 , comprising growing the nucleation layer and the III-V layer by halide vapor phase epitaxy. 38. The method of claim 18 , comprising growing the nucleation layer and the III-V layer by physical vapor deposition. 39. The semiconductor of claim 1 , wherein: a topmost layer of the substrate is silicon, and the nucleation layer is silicon. 40. The method of claim 18 , wherein: a topmost layer of the substrate is silicon, and the nucleation layer is silicon.

Assignees

Inventors

Classifications

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9917156B1 cover?
Nucleation layers for growth of III-nitride structures, and methods for growing the nucleation layers, are described herein. A semiconductor can include a silicon substrate and a nucleation layer over the silicon substrate. The nucleation layer can include silicon and deep-level dopants. The semiconductor can include a III-nitride layer formed over the nucleation layer. At least one of the sili…
Who is the assignee on this patent?
Iqe Plc
What technology area does this patent fall under?
Primary CPC classification H10P14/3216. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 13 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).