Integrated magnetic tunnel junction (MTJ) in back end of line (BEOL) interconnects

Patent metadata

Field	Value
Publication number	US-9917137-B1
Application number	US-201715403452-A
Country	US
Kind code	B1
Filing date	Jan 11, 2017
Priority date	Jan 11, 2017
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A method is presented for forming a semiconductor structure. The method includes depositing a barrier layer, such as a tantalum nitride (TaN) layer, over a dielectric incorporating magnetic random access memory (MRAM) regions, forming magnetic tunnel junction (MTJ) stacks over portions of the TaN layer, patterning and encapsulating the MTJ stacks, forming spacers adjacent the MTJ stacks, and laterally etching sections of the TaN layer, after spacer formation, to form an electrode under the MTJ stacks. The electrode protects the MRAM regions. The electrode can be recessed from the spacers.

First claim

What is claimed is:

1. A method for forming a semiconductor structure, the method comprising:
depositing a barrier layer over a dielectric incorporating magnetic random access memory (MRAM) regions;
forming magnetic tunnel junction (MTJ) stacks over portions of the barrier layer;
patterning and encapsulating the MTJ stacks;
forming spacers adjacent the MTJ stacks; and
laterally etching sections of the barrier layer, after spacer formation, to form an electrode directly contacting the MTJ stacks above the barrier layer and the MRAM regions below the barrier layer.

2. The method of claim 1 , wherein the electrode protects the MRAM regions.

3. The method of claim 1 , wherein the electrode is recessed from the spacers.

4. The method of claim 1 , wherein a low temperature oxide (LTO) layer is deposited after formation of the MTJ stacks.

5. The method of claim 1 , wherein the spacers are composed of a single material.

6. The method of claim 1 , wherein the spacers are composed of multiple materials.

7. The method of claim 1 , wherein the spacers define an L-shaped configuration.

8. The method of claim 1 , wherein the barrier layer is a tantalum nitride (TaN) layer.

9. The method of claim 1 , further comprising creating airgaps via dielectric deposition with pinch-off to reduce capacitive coupling.

10. The method of claim 1 , wherein a width of the electrode is greater than a width of the MRAM region.

11. A semiconductor structure comprising:
a barrier layer deposited over a dielectric incorporating magnetic random access memory (MRAM) regions;
magnetic tunnel junction (MTJ) stacks deposited over portions of the barrier layer, the MTJ stacks patterned and encapsulated; and
spacers formed adjacent the MTJ stacks;
wherein sections of the barrier layer are laterally etched to form an electrode directly contacting the MTJ stacks above the barrier layer and the MRAM regions below the barrier layer.

12. The structure of claim 11 , wherein the electrode protects the MRAM regions.

13. The structure of claim 11 , wherein the electrode is recessed from the spacers.

14. The structure of claim 11 , wherein a low temperature oxide (LTO) layer is deposited after formation of the MTJ stacks.

15. The structure of claim 11 , wherein the spacers are composed of a single material.

16. The structure of claim 11 , wherein the spacers are composed of multiple materials.

17. The structure of claim 11 , wherein the spacers define an L-shaped configuration.

18. The structure of claim 11 , wherein the barrier layer is a tantalum nitride (TaN) layer.

19. The structure of claim 11 , further comprising creating airgaps via dielectric deposition with pinch-off to reduce capacitive coupling.

20. The structure of claim 11 , wherein a width of the electrode is greater than a width of the MRAM region.

Assignees

• IBM

Inventors

• Briggs Benjamin D
• Rizzolo Michael
• Standaert Theodorus E

Classifications

• H10P90/126

  by chemical etching · CPC title

• H10P72/0418

  for etching · CPC title

• H10P50/28

  of insulating materials · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H01L21/0475

  Electricity · mapped topic