Semiconductor device, manufacturing method thereof, and electronic apparatus

Patent metadata

Field	Value
Publication number	US-9917128-B2
Application number	US-201715482561-A
Country	US
Kind code	B2
Filing date	Apr 7, 2017
Priority date	Oct 29, 2009
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.

First claim

What is claimed is:

1. An imaging device comprising:
a first semiconductor section including a first multilayer wiring layer at one side thereof, the first semiconductor section further including a plurality of pixel units arranged in a two-dimensional array, and each pixel unit of the plurality of pixel units including a photodiode and at least one transistor;
a second semiconductor section including a second multilayer wiring layer at one side thereof, the first and second semiconductor sections being secured together with a bonding layer between the first and second multilayer wiring layers such that the respective first and second multilayer wiring layers of the first and second semiconductor sections face each other;
a first conductor extending through the first semiconductor section and the bonding layer to a first portion of the second multilayer wiring layer of the second semiconductor section and electrically interconnecting a wiring of the first multilayer wiring layer with a wiring of the second multilayer wiring layer;
a second conductor extending through the first semiconductor section and the bonding layer to a second portion of the second multilayer wiring layer of the second semiconductor section and electrically interconnecting the wiring of the second multilayer wiring layer with an external wire,
wherein,
the first portion and the second portion of the second multilayer wiring layer are disposed at a same layer.

2. The imaging device of claim 1 , wherein the first conductor includes a metal material.

3. The imaging device of claim 2 , wherein the metal material includes tungsten (W).

4. The imaging device of claim 1 , wherein the second conductor includes a metal material.

5. The imaging device of claim 1 , wherein the second conductor includes one or more of a bonding wire or a solder bump.

6. The imaging device of claim 1 , wherein the first conductor and the second conductor are disposed in a peripheral region around the plurality of pixel units.

7. The imaging device of claim 1 , wherein the first conductor is disposed in a groove portion and the first conductor contacts an insulating layer at a side wall of the groove portion.

8. The imaging device of claim 1 , wherein the first conductor is disposed between a first part of an insulating spacer layer and a second part of the insulating spacer layer in a cross-sectional view.

9. The imaging device of claim 1 , wherein the second wiring layer includes a barrier metal layer.

10. The imaging device of claim 9 , wherein the barrier metal layer includes one or more of TiN, Ti, TaN, or Ta.

11. The imaging device of claim 1 , wherein the bonding layer includes an adhesive layer.

12. The imaging device of claim 1 , wherein the bonding layer includes one or more of a plasma TEOS film, a plasma SiN film, a SiON film, or a SiC film.

13. The imaging device of claim 1 , further comprising:
a stress reduction film disposed between the first semiconductor section and the second semiconductor section.

14. The imaging device of claim 1 , wherein a first pixel unit is separated from a second pixel unit by an isolation region.

15. The imaging device of claim 14 , wherein the first conductor is disposed between a first part of the isolation region and a second part of the isolation region.

16. The imaging device of claim 15 , wherein the isolation region contacts a third part of an insulating spacer layer in the cross-sectional view.

17. The imaging device of claim 1 , further comprising:
a planarization film disposed above the first semiconductor section.

18. The imaging device of claim 1 , further comprising:
a transfer transistor coupled to the photodiode in the first semiconductor section.

19. The imaging device of claim 18 , wherein the transfer transistor is coupled to the first multilayer wiring layer.

20. The imaging device of claim 19 , further comprising:
an on-chip lens and an on-chip color filter disposed above the photodiode.

21. The imaging device of claim 19 , wherein a drain or source region of the transfer transistor is a floating diffusion in the first semiconductor section.

22. The imaging device of claim 19 , further comprising:
a gate electrode disposed in the first semiconductor section.

23. An apparatus comprising:
an imaging device comprising:
a first semiconductor section including a first multilayer wiring layer at one side thereof, the first semiconductor section further including a plurality of pixel units arranged in a two-dimensional array, and each pixel unit of the plurality of pixel units including a photodiode and at least one transistor,
a second semiconductor section including a second multilayer wiring layer at one side thereof, the first and second semiconductor sections being secured together with a bonding layer between the first and second multilayer wiring layers such that the respective first and second multilayer wiring layers of the first and second semiconductor sections face each other,
a first conductor extending through the first semiconductor section and the bonding layer to a first portion of the second multilayer wiring layer of the second semiconductor section and electrically interconnecting a wiring of the first multilayer wiring layer with a wiring of the second multilayer wiring layer;
a second conductor extending through the first semiconductor section and the bonding layer to a second portion of the second multilayer wiring layer of the second semiconductor section and electrically interconnecting the wiring of the second multilayer wiring with an external wire,
wherein the first portion and the second portion of the second multilayer wiring layer are disposed at a same layer; and

at least one lens disposed above the imaging device.

Assignees

• Sony Corp

Inventors

• Takahashi Hiroshi
• Umebayashi Taku

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1914

  using bonding · CPC title

• H10W72/5525

  comprising copper [Cu] · CPC title

• H10W72/5524

  comprising aluminium [Al] · CPC title

• H10W72/983

  Reinforcing structures, e.g. collars · CPC title