Semiconductor structure and method of forming the same

Patent metadata

Field	Value
Publication number	US-9608062-B1
Application number	US-201615250924-A
Country	US
Kind code	B1
Filing date	Aug 30, 2016
Priority date	Aug 3, 2016
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

The present invention provides a semiconductor structure including a fin structure formed on a substrate, and an isolation structure formed in the fin structure. The isolation structure includes a trench, and a first dielectric layer disposed in the trench wherein the first dielectric layer includes a body portion in the bottom, a protruding portion in the top with a top surface, and a shoulder portion connecting the body portion and the protruding portion. The protruding portion has a smaller width than the body portion. The semiconductor structure further includes a second dielectric layer covering a top corner of the trench and sandwiched between the protruding portion, the shoulder portion of the first dielectric layer and the upper sidewall of the trench.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a fin structure disposed on a substrate; and
an isolation structure formed in the fin structure, comprising:
a trench;
a first dielectric layer disposed in the trench, comprising a body portion in the bottom, a protruding portion in the top with a top surface, and a shoulder portion connecting the body portion and the protruding portion, wherein the protruding portion has a smaller width than the body portion; and
a second dielectric layer, covering a top corner of the trench and sandwiched in between the protruding portion and the shoulder portion of the first dielectric layer and an upper sidewall of the trench.

2. The semiconductor structure according to claim 1 , further comprising an inter-fin isolation structure, encompassing the fin structure along a longitudinal direction of the fin structure, wherein the inter-fin isolation structure comprises an inter-fin trench and a dielectric layer filling the inter-fin trench.

3. The semiconductor structure according to claim 2 , wherein the trench and the inter-fin trench have the same depth.

4. The semiconductor structure according to claim 1 , wherein a seam is formed in the middle of the first dielectric layer and extending along the depth direction of the trench.

5. The semiconductor structure according to claim 4 , wherein the first dielectric layer comprises silicon nitride.

6. The semiconductor structure according to claim 1 , further comprising a liner disposed between the body portion and a lower sidewall of the trench, wherein the protruding portion is not in direct contact with the liner.

7. The semiconductor structure according to claim 6 , wherein the second dielectric layer is thicker than the liner.

8. The semiconductor structure according to claim 1 , wherein the top surface of the protruding portion is lower than the fin structure by 10 to 100 angstroms.

9. The semiconductor structure according to claim 1 , further comprising a gate structure, comprising:
a gate body, disposed on the fin structure, aligned with the trench and completely covering the trench;
a spacer, disposed on two opposite sidewalls of the gate body; and
a gate dielectric layer, disposed between the spacer and the fin structure.

10. The semiconductor structure according to claim 9 , wherein the gate body fills an upper portion of the trench, and the second dielectric layer is sandwiched in between the gate body of the gate structure, the protruding portion and the shoulder portion of the first dielectric layer and the upper sidewall of the trench.

11. The semiconductor structure according to claim 10 , wherein the gate body comprises a metal, and the second dielectric layer comprises an interfacial layer and a high-k dielectric layer.

12. The semiconductor structure according to claim 11 , wherein the interfacial layer covers the top corner and the upper sidewall of the trench, and the high-k dielectric layer covers the interfacial layer and the top surface of the protruding portion of the first dielectric layer.

13. The semiconductor structure according to claim 9 , further comprising a source/drain region, formed in the fin structure at each side of the gate structure and adjacent to the trench, wherein a bottom portion of the source/drain region is lower than the shoulder portion of the first dielectric layer.

14. A method of forming a semiconductor structure, comprising:
providing a fin structure formed on a substrate;
forming a trench in the fin structure;
forming a first dielectric layer filling the trench, wherein the first dielectric layer comprises a body portion in the bottom, a protruding portion in the top and a shoulder portion connecting the body portion and the protruding portion; and
forming a second dielectric layer, covering a top corner of the trench and sandwiched in between the protruding portion and the shoulder portion of the first dielectric layer and an upper sidewall of the trench.

15. The method of forming a semiconductor structure according to claim 14 , further comprising forming an inter-fin isolation structure, encompassing the fin structure along a longitudinal direction of the fin structure.

16. The method of forming a semiconductor structure according to claim 14 , wherein the first dielectric layer is formed by the atomic layer deposition (ALD) process.

17. The method of forming a semiconductor structure according to claim 16 , wherein the first dielectric layer comprises silicon nitride.

18. The method of forming a semiconductor structure according to claim 14 , further comprising forming a liner on a surface of the trench before forming the first dielectric layer.

19. The method of forming a semiconductor structure according to claim 14 , further comprising forming a gate structure, wherein the gate structure comprises a gate body aligned with and completely covering the trench and filling into an upper portion of the trench, and the second dielectric layer is sandwiched in between the gate body of the gate structure, the protruding portion and the shoulder portion of the first dielectric layer and the upper sidewall of the trench.

20. The method of forming a semiconductor structure according to claim 19 , further comprising forming a source/drain region in the fin structure at each side of the gate structure.

Assignees

• United Microelectronics Corp

Inventors

• Tseng I-Ming
• Liang Wen-An
• Huang Chen-Ming

Classifications

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10D30/6211

  having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates · CPC title