Semiconductor device including finFET and fin varactor

Patent metadata

Field	Value
Publication number	US-9917081-B2
Application number	US-201615181676-A
Country	US
Kind code	B2
Filing date	Jun 14, 2016
Priority date	Nov 30, 2015
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate including a first region and a second region;
a fin-type field effect transistor (finFET) including a first semiconductor fin on an upper surface of the first region, the first semiconductor fin extending from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height; and
a fin varactor including a second semiconductor fin on an upper surface of the second region, the second semiconductor fin having uniform sidewalls extending from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET; and
a doped punchthrough stop (PTS) layer beneath each of the first semiconductor fin and the second semiconductor fin, wherein a first portion of the PTS layer extends from the upper surface of the first region into the semiconductor substrate at a distance to define a first PTS height, and a second portion of the PTS layer extends from the upper surface of the second region into the semiconductor substrate at the distance to define a second PTS height that matches the first height,
wherein the second semiconductor fin is entirely doped thereby defining a doped varactor portion having a first thickness, and
wherein the first semiconductor fin includes an upper fin portion having a first fin thickness, and a lower fin portion interposed between the upper fin portion and the upper surface of the first region, the lower fin portion having a second fin thickness that is different from the first fin thickness and that is entirely doped, and having a lower portion height extending from the upper fin portion and the upper surface of the first region,
wherein a first total size of the lower fin portion defined by the lower portion height and the second fin thickness is greater than a second total size of the varactor portion defined by the second total fin height and the first thickness such that a first body resistance of the finFET is greater than a second body resistance of the fin varactor.

2. The semiconductor device of claim 1 , wherein the second total fin height is less than the first total fin height.

3. The semiconductor device of claim 1 , wherein the finFET has a first body resistance defined by the upper thickness and the lower thickness, and the fin varactor has a second body resistance defined by the varactor thickness, the second body resistance being less than the first body resistance.

4. A semiconductor device, comprising:
a semiconductor substrate including a first region and a second region;
a fin-type field effect transistor (finFET) including a first semiconductor fin on an upper surface of the first region, the first semiconductor fin including a lower doped portion interposed between an upper undoped portion and the upper surface;
a fin varactor including a second semiconductor fin having a single doped portion formed directly on an upper surface of the second region, the fin varactor having uniform sidewalls that extend from the upper surface of the second region to an upper surface of the fin varactor; and
a doped punchthrough stop (PTS) layer beneath each of the first semiconductor fin and the second semiconductor fin, wherein a first portion of the PTS layer extends from the upper surface of the first region into the semiconductor substrate at a distance to define a first PTS height, and a second portion of the PTS layer extends from the upper surface of the second region into the semiconductor substrate at the distance to define a second PTS height that matches the first height,
wherein the lower doped portion extends continuously from the upper undoped portion to the bottom of the first semiconductor fin and contacts the PTS layer.

5. The semiconductor device of claim 4 , wherein the first semiconductor fin extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height, and the second semiconductor fin extending from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.

6. The semiconductor device of claim 5 , wherein the second total fin height is less than the first total fin height.

7. The semiconductor device of claim 4 , wherein the finFET has a first body resistance and the fin varactor has a second body resistance that is less than the first body resistance.

8. A semiconductor device, comprising:
a semiconductor substrate including a varactor region and a transistor region;
a fin varactor including at least one first semiconductor fin on an upper surface of the varactor region, the at least one first semiconductor fin having uniform sidewalls extending uniformly from an upper varactor fin surface thereof to the upper surface of the varactor region to define a single thickness between opposing respective sidewalls; and
a fin-type field effect transistor (finFET) including at least one second semiconductor fin on an upper surface of the transistor region, the at least one second semiconductor fin extending non-uniformly from an upper finFET surface thereof to the upper surface of the transistor region so as to define different thicknesses between respective opposing sidewalls; and
a doped punchthrough stop (PTS) layer beneath each of the at least one first semiconductor fin and the at least one second semiconductor fin, wherein a varactor portion of the PTS layer extends from the upper surface of the varactor region into the semiconductor substrate at a distance to define a first PTS height, and a finFET portion of the PTS layer extends from the upper surface of the transistor region into the semiconductor substrate at the distance to define a second PTS height, wherein the first height of the varactor portion matches the second height of the finFET portion,
wherein the non-uninform extension includes a first portion on an upper surface of a second portion, the first portion having a first uniform thickness between respective opposing sidewalls and the second portion having a second uniform thickness different from the first uniform thickness such that the difference between the first uniform thickness and the second uniform thickness defines the non-uniform extension of the at least one second semiconductor fin.

9. The semiconductor device of claim 8 , wherein the distance between the upper varactor fin surface and the upper surface of the varactor region defines a first total height, and the distance between the upper finFET surface and the upper surface of the transistor region defines a second height that is different than the first height.

10. The semiconductor device of claim 9 , wherein the second thickness is greater than both the first thickness of the first portion and the single thickness of the at least one first semiconductor fin.

11. The semiconductor device of claim 10 , wherein the entire at least one first semiconductor fin is doped, and wherein the second portion of the at least one second semiconductor fin is entirely doped while the first portion of the at least one second semiconductor fin is un-doped.

12. The semiconductor device of claim 9 , wherein the second total fin height is less than the first total fin height.

13. The semiconductor device of claim 8 , wherein the finFET has a first body resistance and the fin varactor has a second body resistance that is less than the first body resistance.

14. The semiconductor device of claim 8 , wherein the at least one first s

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Cheng Kangguo
• Wang Junli
• Xie Ruilong
• Yamashita Tenko

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H01L29/93

  Electricity · mapped topic

• H01L29/785

  Electricity · mapped topic

• H01L29/1083

  Electricity · mapped topic