Semiconductor device including source/drain contact having height below gate stack

Patent metadata

Field	Value
Publication number	US-9917050-B2
Application number	US-201615331363-A
Country	US
Kind code	B2
Filing date	Oct 21, 2016
Priority date	May 16, 2014
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A semiconductor device includes a substrate having source and drain regions, and a channel region arranged between the source and drain regions. The device further includes a gate structure over the substrate and adjacent to the channel region. The gate structure includes a gate stack, a spacer on sidewalls of the gate stack, and a conductor over the gate stack. The device further includes a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions. A top surface of the first contact feature is lower than a top surface of the gate structure. The device further includes a first dielectric layer over the first contact feature. A top surface of the first dielectric layer is below or substantially co-planar with the top surface of the gate structure. The conductor at most partially overlaps in plan view with the first dielectric layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate having a source region and a drain region;

a channel region arranged between the source and drain regions;
a gate structure over the substrate and adjacent to the channel region, wherein the gate structure includes a gate stack, a spacer on at least sidewalls of the gate stack, and a conductor over the gate stack;
a first contact feature over the substrate and electrically connecting to at least one of the source and drain regions, a top surface of the first contact feature being lower than a top surface of the gate structure; and
a first dielectric layer over the first contact feature, the first dielectric layer in physical contact with and at least partially covering the first contact feature, a top surface of the first dielectric layer being below or substantially co-planar with the top surface of the gate structure, wherein the conductor at most partially overlaps in plan view with the first dielectric layer, and wherein the conductor does not physically contact the first dielectric layer.

2. The semiconductor device of claim 1 , wherein the first dielectric layer has a thickness that is 0.2˜4 times of a height of the gate stack.

3. The semiconductor device of claim 1 , wherein:
the gate stack has a first dimension along a gate length direction of the semiconductor device;
the first contact feature has a second dimension along a gate width direction of the semiconductor device; and
the second dimension is greater than 1.6 times of the first dimension.

4. The semiconductor device of claim 1 , further comprising:
an inter-layer dielectric (ILD) layer over the gate structure and the first dielectric layer; and
a via penetrating the ILD layer and electrically contacting the conductor, wherein the via overlaps the channel region in the plan view.

5. The semiconductor device of claim 4 , wherein the first dielectric layer is configured to protect the first contact feature from being electrically connected to the via during manufacturing of the semiconductor device.

6. The semiconductor device of claim 4 , further comprising:
a second source/drain region in another portion of the substrate;
a second contact feature over the second source/drain region and electrically connecting to the second source/drain region, the second contact feature being of substantially the same height as the first contact feature; and
a third contact feature directly contacting the first and second contact features and partially overlapping the first and second contact features in the plan view.

7. The semiconductor device of claim 6 , wherein the third contact feature has a smaller dimension than the first contact feature in a gate length direction of the semiconductor device.

8. The semiconductor device of claim 6 , wherein a top surface of the third contact feature is lower than a top surface of the via.

9. The semiconductor device of claim 1 , wherein the conductor does not overlap in the plan view with the first dielectric layer, and wherein a top surface of the first dielectric layer is below the top surface of the gate structure.

10. The semiconductor device of claim 1 , wherein the first contact feature includes aluminum, tungsten, copper, or cobalt; and wherein the first dielectric layer includes titanium oxide, silicon oxide, silicon oxynitride, or silicon nitride.

11. The semiconductor device of claim 1 , wherein the first dielectric layer and the spacer comprise different materials.

12. A semiconductor device, comprising:
a substrate having source and drain regions;

a channel region arranged between the source and drain regions;
a gate structure over the channel region, wherein the gate structure includes a gate stack, a spacer on at least sidewalls of the gate stack, and a first conductor over the gate stack;
a second conductor over and electrically connecting to at least one of the source and drain regions, a top surface of the second conductor being lower than a top surface of the spacer;
a first dielectric layer over the second conductor, a top surface of the first dielectric layer being substantially co-planar with the top surface of the spacer, wherein the first conductor does not physically contact the first dielectric layer;

an inter-layer dielectric (ILD) layer over the gate structure and the first dielectric layer; and
a via going through the ILD layer and electrically contacting the first conductor, wherein the via overlaps the channel region in the plan view.

13. The semiconductor device of claim 12 , wherein the first dielectric layer and the spacer comprise different materials.

14. The semiconductor device of claim 12 , wherein the first dielectric layer includes titanium oxide, silicon oxide, silicon oxynitride, or silicon nitride.

15. The semiconductor device of claim 12 , wherein the first dielectric layer has a thickness that is 0.2˜4 times of a height of the gate stack.

16. The semiconductor device of claim 13 , further comprising a third conductor over and electrically connecting to the second conductor, wherein a lower portion of the third conductor is in the first dielectric layer and an upper portion of the third conductor is above the first dielectric layer.

17. The semiconductor device of claim 16 , wherein a top surface of the third conductor is below a top surface of the via.

18. The semiconductor device of claim 17 , further comprising a barrier layer on sidewalls and the top surface of the third conductor.

19. A semiconductor device, comprising:
a substrate having two source/drain regions;

a channel region between the source/drain regions;
a gate structure over the channel region, wherein the gate structure includes a gate stack, a spacer on at least sidewalls of the gate stack, and a first conductor over the gate stack and between opposing sidewalls of the spacer;
a second conductor over and electrically connecting to at least one of the source/drain regions, a top surface of the second conductor being lower than a top surface of the spacer;
a first dielectric layer over the second conductor, a top surface of the first dielectric layer being below or substantially co-planar with the top surface of the spacer, wherein the first conductor does not overlap in plan view with the first dielectric layer, and wherein the first dielectric layer and the spacer comprise different materials;
an inter-layer dielectric (ILD) layer over the gate structure and the first dielectric layer;
a via going through the ILD layer and electrically contacting the first conductor, wherein the via overlaps the channel region in the plan view; and
a third conductor electrically connecting to the second conductor, wherein the third conductor is partially embedded in the first dielectric layer.

20. The semiconductor device of claim 19 , wherein a top surface of the third conductor is lower than a top surface of the via.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Chih-Liang
• Lai Chih-Ming
• Sio Kam-Tou
• Liu Ru-Gun
• Shen Meng-Hung
• Liou Chun-Hung
• Sung Shu-Hui
• Young Charles Chew-Yuen

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/092

  by smoothing the dielectric parts · CPC title

• H10W20/074

  of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers · CPC title