Package with bi-layered dielectric structure

US9917044B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9917044-B2
Application numberUS-201515028278-A
CountryUS
Kind codeB2
Filing dateMay 13, 2015
Priority dateMay 13, 2015
Publication dateMar 13, 2018
Grant dateMar 13, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Some embodiments of the present disclosure describe a multi-layer package with a bi-layered dielectric structure and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a dielectric structure coupled with a metal layer, with the dielectric structure including a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a thickness less than a thickness of the second dielectric layer and a dielectric loss tangent greater than a dielectric loss tangent of the second layer. Other embodiments may be described and/or claimed.

First claim

Opening claim text (preview).

What is claimed is: 1. An integrated circuit (IC) package assembly comprising: a dielectric structure coupled with a metal layer, wherein the dielectric structure includes: a first dielectric layer having a first side and a second side opposite to the first side, wherein a distance between the first and second sides of the first dielectric layer defines a first thickness, and wherein the first dielectric layer has a first dielectric loss tangent; and a second dielectric layer having a first side and a second side opposite to the first side, wherein a distance between the first and second sides of the second dielectric layer defines a second thickness, and wherein the second dielectric layer has a second dielectric loss tangent; and a solder mask layer coupled with the dielectric structure, wherein the first side of the first dielectric layer is directly coupled with the second side of the second dielectric layer, the metal layer is coupled with the second side of the first dielectric layer, the first dielectric loss tangent is greater than the second dielectric loss tangent, and the first thickness is less than the second thickness. 2. The IC package assembly of claim 1 , wherein the first thickness is greater than or equal to 1 micron and less than or equal to 5 microns. 3. The IC package assembly of claim 1 , wherein: the first dielectric layer is formed of a first set of molecules and the second dielectric layer is formed of a second set of molecules; and molecules in the first set of molecules have a greater electric molecular dipole moment than molecules in the second set of molecules. 4. The IC package assembly of claim 1 , wherein the first dielectric layer has a dielectric loss tangent greater than 0.005 for operation in a range from greater than or equal to 1 gigahertz to less than or equal to 50 gigahertz. 5. The IC package assembly of claim 1 , wherein the second dielectric layer has a dielectric loss tangent less than 0.003 for operation in a range from greater than or equal to 1 gigahertz to less than or equal to 50 gigahertz. 6. The IC package assembly of claim 1 , further comprising a via structure extending through the first dielectric layer and the second dielectric layer of the dielectric structure. 7. The IC package assembly of claim 6 , wherein the metal layer is a first metal layer, the IC package assembly further comprising a second metal layer having a first side coupled with the first side of the second dielectric layer. 8. The IC package assembly of claim 7 , wherein the dielectric structure is a first dielectric structure, the IC package assembly further comprising a second dielectric structure, wherein the second dielectric structure includes: a first dielectric layer having a first side and a second side opposite to the first side, wherein a distance between the first and second sides of the first dielectric layer of the second dielectric structure defines a first thickness, and wherein the first dielectric layer of the second dielectric structure has a first dielectric loss tangent; and a second dielectric layer having a first side and a second side opposite to the first side, wherein a distance between the first and second sides of the second dielectric layer of the second dielectric structure defines a second thickness, and wherein the second dielectric layer of the second dielectric structure has a second dielectric loss tangent, wherein: the first side of the first dielectric layer of the second dielectric structure is coupled with the second side of the second dielectric layer of the second dielectric structure; the second side of the first dielectric layer of the second dielectric structure is coupled with a second side of the second metal layer; the first dielectric loss tangent of the second dielectric structure is greater than the second dielectric loss tangent of the second dielectric structure; and the first thickness of the second dielectric structure is less than the second thickness of the second dielectric structure. 9. The IC package assembly of claim 8 , wherein: the via structure is a first via structure extending through the first dielectric layer and the second dielectric layer of the first dielectric structure; and the IC package assembly further comprises a second via structure extending through the first dielectric layer and the second dielectric layer of the second dielectric structure. 10. The IC package assembly of claim 9 , wherein the first via structure is electrically coupled with the second via structure. 11. A method of fabricating an integrated circuit (IC) package assembly, the method comprising: providing a dielectric structure including a first dielectric layer having a first side and a second side opposite to the first side, wherein the dielectric structure includes a second dielectric layer, the second dielectric layer having a first side and a second side opposite to the first side; and coupling a metal layer of a metal covered core with the second side of the first dielectric layer, wherein: a core layer of the metal covered core includes a dielectric material; a distance between the first and second sides of the first dielectric layer defines a first thickness; the first dielectric layer has a first dielectric loss tangent; a distance between the first and second sides of the second dielectric layer defines a second thickness; the second dielectric layer has a second dielectric loss tangent; the first side of the first dielectric layer is coupled with the second side of the second dielectric layer; the first thickness is less than the second thickness; and the first dielectric loss tangent is greater than the second dielectric loss tangent. 12. The method of claim 11 , wherein the first dielectric layer has a thickness between greater than or equal to 1 micron and less than or equal to 5 microns. 13. The method of claim 11 , wherein: the first dielectric layer is formed of a first set of molecules; the second dielectric layer is formed of a second set of molecules; and molecules in the first set of molecules have a greater electric molecular dipole moment than molecules in the second set of molecules. 14. The method of claim 11 , wherein the first dielectric layer has a dielectric loss tangent greater than 0.005 for operation in a range from greater than or equal to 1 gigahertz to less than or equal to 50 gigahertz. 15. The method of claim 11 , wherein the second dielectric layer has a dielectric loss tangent less than 0.003 for operation in a range from greater than or equal to 1 to less than or equal to 50 gigahertz. 16. The method of claim 11 , further comprising forming an opening for a via through the dielectric structure. 17. The method of claim 16 , wherein forming an opening includes performing a laser drilling process. 18. The method of claim 16 , further comprising desmearing the opening. 19. The method of claim 16 , further comprising depositing a metal to fill the opening. 20. The method of claim 19 , wherein the dielectric structure is a first dielectric structure, wherein the metal layer is a first metal layer, and the method further comprises: coupling a second metal layer with the second dielectric layer of the first dielectric structure; and coupling a first dielectric layer of a second dielectric structure with the second metal layer, wherein: the first dielectric layer of the second dielectric structure has a first side and a second side opposite to the first side; a distance between the

Assignees

Inventors

Classifications

  • on active surfaces of flip-chip devices, e.g. underfills · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • Organic materials · CPC title

  • for antennas · CPC title

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What does patent US9917044B2 cover?
Some embodiments of the present disclosure describe a multi-layer package with a bi-layered dielectric structure and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a dielectric structure coupled with a metal layer, with the dielectric structure including a first dielectric layer and a second dielectric layer, wherein the first d…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W70/685. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 13 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).