Predictive multistage comparison for associative memory

Patent metadata

Field	Value
Publication number	US-9916246-B1
Application number	US-201615238209-A
Country	US
Kind code	B1
Filing date	Aug 16, 2016
Priority date	Aug 16, 2016
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A processing system includes a shadow tag memory, which stores a plurality of entries containing coherency information for the cachelines residing at the various levels of private caches. If a cache miss occurs at a private cache, or if coherency information for a cacheline requires updating, a probe is sent to the shadow tag memory maintained at the shared cache to determine whether the requested (or affected) cacheline is stored at another private cache. The probe includes a tag which can be divided into two or more portions. To more efficiently compare the probe tag to the shadow tag entries, the comparison is performed in multiple stages based on the portions of the probe tag.

First claim

What is claimed is:

1. A method, comprising:
in response to receiving, at a first cache shared by a plurality of processor cores, a cache probe comprising a first tag associated with a first memory address:
responsive to a comparison of a first portion of the first tag matching a first portion of at least one entry of a shadow tag memory, comparing a second portion of the first tag to a plurality of second portions of entries of the shadow tag memory to identify coherency information for an entry of a second cache.

2. The method of claim 1 , further comprising:
responsive to the comparison of the first portion of the first tag not matching the first portion of at least one entry of the shadow tag memory, indicating a cache miss at the first cache.

3. The method of claim 2 , further comprising:
in response to the second portion of the first tag not matching a second portion of at least one entry of the shadow tag memory, indicating a cache miss at the first cache.

4. The method of claim 1 , further comprising:
responsive to the first portion of the first tag matching the first portion of at least one entry of the shadow tag memory and the second portion of the first tag matching a second portion of at least one entry of the shadow tag memory, identifying the second cache from a plurality of caches and forwarding the cache probe to the identified second cache.

5. The method of claim 4 wherein the plurality of caches comprises a plurality of private caches, each of the plurality of private caches dedicated to a different one of the plurality of processor cores.

6. The method of claim 5 , wherein the cache probe originates from one of the plurality of private caches.

7. The method of claim 6 , further comprising excluding from comparison to the cache probe a subset of shadow tag memory entries associated with the private cache from which the cache probe originated.

8. The method of claim 1 , wherein the first portion of the first tag comprises a number of least significant bits of the first tag.

9. The method of claim 1 , wherein the second portion of the first tag comprises tag bits not included in the first portion of the first tag.

10. A method, comprising:
comparing first portions of entries of a shadow tag memory of a shared cache shared by a plurality of processor cores to a first portion of a tag for a cache probe associated with a cacheline;
responsive to matching at least one entry of the shadow tag memory to the first portion of the tag, comparing a second portion of the at least one matching entry to a second portion of the tag; and
responsive to determining the shadow tag memory has an entry matching the first and second portions of the tag for the cacheline, identifying a private cache associated with the matching entry and forwarding the cache probe to the identified private cache.

11. The method of claim 10 , further comprising:
responsive to determining that the shadow tag memory does not have at least one entry matching the first portion of the tag, signaling a cache miss in response to the cache probe.

12. The method of claim 10 , further comprising:
responsive to determining the shadow tag memory does not have a valid entry matching the first and second portions of the tag for the cacheline, signaling a cache miss in response to the cache probe.

13. The method of claim 10 , wherein the first portion of the tag comprises a number of least significant bits of the tag.

14. The method of claim 10 , wherein the second portion of the tag comprises tag bits not included in the first portion of the tag.

15. A processing system, comprising:
a plurality of private caches, each private cache associated with a corresponding processor core of a plurality of processor cores and comprising a corresponding set of cachelines;
a shared cache shared by the plurality of processor cores, the shared cache comprising a shadow tag memory comprising a plurality of entries, each entry storing state and address information for a corresponding cacheline of the set of cachelines of one of the private caches; and
a multistage compare module comprising:
a first stage compare module configured to compare first portions of the entries of the shadow tag memory to a first portion of a tag for cache probe associated with a cacheline;
a second stage compare module configured to compare second portions of entries matching the first portion of the tag to a second portion of the tag; and
wherein the multistage compare module is configured to identify coherency information for a cacheline associated with an entry of the shadow tag memory matching the first and second portions of the tag for the cacheline.

16. The processing system of claim 15 , wherein the multistage compare module is configured to signal a cache miss in response to the cache probe, responsive to determining that the shadow tag memory does not have at least one entry matching the first portion of the tag.

17. The processing system of claim 16 , wherein the multistage compare module is configured to signal a cache miss in response to the cache probe, responsive to determining that the shadow tag memory does not have at least one entry matching the second portion of the tag.

18. The processing system of claim 15 , wherein the first portion of the tag comprises a number of least significant bits of the tag.

19. The processing system of claim 15 , wherein the second portion of the tag comprises tag bits not included in the first portion of the tag.

20. The processing system of claim 15 , wherein the cache probe originates from one of the plurality of private caches.

Assignees

• Advanced Micro Devices Inc

Inventors

• Henrion Carson Donahue
• Ciraula Michael K
• Donley Gregg
• Garg Alok
• Busta Eric

Classifications

• G06F2212/69

  Physics · mapped topic

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F12/128

  adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel · CPC title

• G06F12/0815

  Cache consistency protocols · CPC title

• G06F12/0811 Primary

  with multilevel cache hierarchies · CPC title