Storage controller caching using symmetric storage class memory devices

Patent metadata

Field	Value
Publication number	US-9916241-B2
Application number	US-201514826870-A
Country	US
Kind code	B2
Filing date	Aug 14, 2015
Priority date	Aug 14, 2015
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

Systems and techniques for performing a data transaction are disclosed that provide data redundancy using two or more cache devices. In some embodiments, a data transaction is received by a storage controller of a storage system from a host system. The storage controller caches data and/or metadata associated with the data transaction to at least two cache devices that are discrete from the storage controller. After caching, the storage controller provides a transaction completion response to the host system from which the transaction was received. In some examples, each of the at least two cache devices includes a storage class memory. In some examples, the storage controller caches metadata to the at least two cache devices and to a controller cache of the storage controller, while data is cached to the at least two cache devices without being cached in the controller cache.

First claim

What is claimed is:

1. A method comprising:
receiving a data transaction, wherein the data transaction is received by a storage controller of a storage system and received from a host system;
caching, by the storage controller, at least one of data or metadata associated with the data transaction into at least two discrete cache devices that are discrete from the storage controller, wherein each of the at least two discrete cache devices is a non-volatile memory device;
concurrently with caching the at least one of data or metadata into the at least two discrete cache devices, caching the metadata into a controller cache of the storage controller; and
after the caching of the at least one of data or metadata to the at least two discrete cache devices, providing a transaction completion response to the host system from which the data transaction is received.

2. The method of claim 1 , wherein the at least two discrete cache devices include storage class memory, and wherein the storage class memory includes at least one of a resistive random access memory (RAM) device, a phase-change RAM device, a flash memory device, or a battery-backed dynamic random access memory (DRAM) device.

3. The method of claim 1 , wherein the at least two discrete cache devices are coupled to the storage controller by a peripheral component interconnect (PCI) Express (PCIe) interface, and wherein the caching of the at least one of data or metadata includes providing the at least one of data or metadata from the storage controller to the at least two discrete cache devices via the PCIe interface.

4. The method of claim 1 , further comprising:
concurrently with caching the metadata to the at least two discrete cache storage devices, storing the in the controller cache of the storage controller.

5. The method of claim 4 , wherein the at least one of data or metadata includes both data and metadata associated with the data transaction.

6. The method of claim 1 , wherein the at least one of data or metadata includes metadata associated with the data transaction, the method further comprising:
caching, by the storage controller, the data associated with the data transaction to the at least two discrete cache devices without storing the data in the controller cache.

7. The method of claim 1 further comprising determining a mapping of an address of the at least two discrete cache devices to an address of a storage device, wherein the caching of the at least one of data or metadata includes caching the mapping to the at least two discrete cache devices.

8. The method of claim 7 further comprising storing the mapping in the controller cache of the storage controller.

9. The computing device of claim 1 , further comprising storing the metadata in the controller cache of the storage controller, wherein the metadata maps address of the at least two discrete cache devices to an address of a storage device.

10. A non-transitory machine readable medium having stored thereon instructions for performing a method of executing a data transaction, comprising machine executable code which when executed by at least one machine, causes the at least one machine to:
receive a data transaction from a host system;
cause a storage controller to concurrently cache an element associated with the data transaction into at least two non-volatile cache devices and into a controller cache associated with the storage controller and that is distinct from the at least two non-volatile cache devices,
wherein the at least two non-volatile cache devices are discrete from the storage controller,
wherein the element is cached to partitions of the at least two non-volatile cache devices, and
wherein the partitions are associated with the storage controller;

after the element is cached, provide a transaction completion response to the host system.

11. The non-transitory machine readable medium of claim 10 comprising further machine executable code that causes the machine to:
when a failure of the storage controller is detected, associate the partitions with another storage controller.

12. The non-transitory machine readable medium of claim 10 , wherein each of the at least two non-volatile cache devices includes a storage class memory, and wherein the code to cause the storage controller to concurrently cache the element includes code to cause the storage controller to provide the element to the storage class memories via a peripheral component interconnect (PCIe) bus.

13. The non-transitory machine readable medium of claim 10 , comprising further machine executable code that causes the storage controller to cache the element in a wherein the controller cache is within the storage controller that is different from the at least two non-volatile cache devices.

14. The non-transitory machine readable medium of claim 13 wherein the element includes metadata associated with the data transaction, the non-transitory machine readable medium comprising further machine executable code that causes the storage controller to cache data associated with the data transaction in the at least two non-volatile cache devices without caching the data in the controller cache.

15. The non-transitory machine readable medium of claim 13 wherein the element includes data and metadata associated with the data transaction.

16. The non-transitory machine readable medium of claim 10 comprising further machine executable code that causes the storage controller to cache, in the at least two non-volatile cache devices, a mapping of an address of the at least two non-volatile cache devices to an address of a storage device.

17. A computing device comprising:
a memory containing machine readable medium comprising machine executable code having stored thereon instructions for performing a method of executing a data transaction;
a processor coupled to the memory, the processor configured to execute the machine executable code to:
receive a transaction from a host;
concurrently cache, using a storage controller, metadata associated with the transaction into at least two non-volatile storage class memories that are distinct from the storage controller and into a controller cache associated with the storage controller; and
concurrently cache, using the storage controller, data associated with the transaction into the at least two non-volatile storage class memories without caching the data in the controller cache.

18. The computing device of claim 17 , wherein the at least two non-volatile storage class memories each include at least one of a resistive RAM device, phase-change RAM device, a flash memory device, or a battery-backed DRAM device.

19. The computing device of claim 17 , wherein the at least two non-volatile storage class memories are coupled to the storage controller by a peripheral component interconnect (PCIe) interface.

20. The computing device of claim 17 , wherein the metadata includes a mapping of an address of the at least two non-volatile storage class memories to an address of a storage device.

Assignees

• Netapp Inc

Inventors

• Mckean Brian
• Friebus Gregory
• Ummadi Sandeep Kumar R
• Ganesan Pradeep

Classifications

• G06F12/0804 Primary

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/312

  In storage controller · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title