Method of producing a cap substrate, and packaged radiation-emitting device

US9912115B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9912115-B2
Application numberUS-201615173110-A
CountryUS
Kind codeB2
Filing dateJun 3, 2016
Priority dateDec 3, 2013
Publication dateMar 6, 2018
Grant dateMar 6, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The invention relates to methods of producing a cap substrate, to methods of producing a packaged radiation-emitting device at the wafer level, and to a radiation-emitting device. By producing a cap substrate, providing a device substrate in the form of a wafer including a multitude of radiation-emitting devices, arranging the substrates one above the other such that the substrates are bonded along an intermediate bonding frame, and dicing the packaged radiation-emitting devices, improved packaged radiation-emitting devices are provided which are advantageously arranged within a cavity free from organics and can be examined, still at the wafer level, in terms of their functionalities in a simplified manner prior to being diced.

First claim

Opening claim text (preview).

The invention claimed is: 1. A method of producing a cap substrate, comprising: providing a mold substrate comprising a structured surface region; arranging a cover substrate on the structured surface region of the mold substrate, the cover substrate comprising a glass material, and connecting the cover substrate to the mold substrate, the structured surface of the mold substrate being brought into contact with a surface of the cover substrate in such a way that they at least partially overlap; forming first island regions and respectively associated adjacent second island regions from the mold substrate, recesses being provided between the first island regions and the respectively associated adjacent second island regions; arranging a window component within a recess of the recesses located between a first island region and the associated adjacent second island region; arranging a carrier substrate on the first island regions and on the second island regions, wherein the first island regions and the second island regions are formed from the mold substrate, so that the first island regions and the second island regions are located between the carrier substrate and the cover substrate; tempering the bonded substrates such that the glass material of the cover substrate is caused to flow into the remaining recesses located between the island regions; and removing the cover substrate from the mold substrate and the carrier substrate so as to achieve the structured cap substrate comprising the window component on a side face of the cap substrate. 2. The method as claimed in claim 1 , wherein said providing of the mold substrate further comprises: providing a semiconductor wafer comprising a passivation layer on a surface; lithographing the passivation layer so that the passivation layer will remain on the surface wherever the first island regions and the second island regions are provided; etching the surface of the semiconductor wafer with regard to the lithographed regions, so that a thickness of the semiconductor wafer is reduced perpendicularly to the lithographed regions of the surface so as to structure the surface region and to thus specify positions for the first island regions and the second island regions; and completely removing the passivation layer. 3. The method as claimed in claim 1 , wherein said arranging and connecting of the cover substrate comprises: anodically bonding, region by region, the structured surface region of the mold substrate with a surface region of the cover substrate. 4. The method as claimed in claim 1 , wherein said arranging of the window component in each case comprises: providing several strip-shaped window components; and inserting the strip-shaped window components into the recesses located between the first island regions and the second island regions, so that surfaces of the window components that are provided as surfaces of optical output windows are located opposite surfaces of the island regions that are formed from the mold substrate. 5. The method as claimed in claim 1 , wherein said arranging of the respective window component comprises: inserting semiconductor strips into the recesses prior to inserting the strip-shaped window components into the recesses, so that the semiconductor strips are arranged between surfaces of the window components that are provided as surfaces of optical output windows, and surfaces of the island regions that are formed from the mold substrate. 6. The method as claimed in claim 1 , wherein said arranging of the respective window component comprises: providing one or more strip-shaped window elements coated with semiconductor material. 7. The method as claimed in claim 1 , wherein said arranging of the window component comprises: cutting to length of strip-shaped window components from a lens array in each case. 8. The method as claimed in claim 1 , wherein the first and second island regions comprise edge chamfers in a region adjacent to the carrier substrate, said tempering comprising the glass material of the window component flowing into the region located between the chamfers and the carrier substrate so as to form a circumferential protrusion from the glass material. 9. The method as claimed in claim 2 , wherein said providing of the mold substrate further comprises: wherein, in lithographing the passivation layer, the passivation layer is further removed from the surface where channel structures are provided within the first and second island regions, wherein during etching of the surface of the semiconductor wafer with regard to the lithographic regions, channels are etched, in addition, into the mold substrate within the first and second island regions. 10. A method of producing a cap substrate, comprising: providing a mold substrate comprising a structured surface region; arranging a carrier substrate on the structured surface region of the mold substrate and connecting the carrier substrate to the mold substrate, the structured surface of the mold substrate being brought into contact with a surface of the carrier substrate in such a way that they at least partially overlap; forming first island regions and respectively associated adjacent second island regions from the mold substrate, recesses being provided between the first island regions and the respectively associated adjacent second island regions; arranging a window component within a recess of the recesses located between a first island region and the associated adjacent second island region; arranging a cover substrate on the first island regions and on the second island regions, wherein the first island regions and the second island regions are formed from the mold substrate, so that the first island regions and the second island regions are located between the carrier substrate and the cover substrate, the cover substrate comprising a glass material; tempering the bonded substrates such that the glass material of the cover substrate is caused to flow into the remaining recesses located between the island regions; and removing the cover substrate from the mold substrate and the carrier substrate so as to achieve the structured cap substrate comprising the window component on a side face of the cap substrate. 11. The method as claimed in claim 10 , wherein said providing of the mold substrate comprises: providing a semiconductor wafer comprising a passivation layer on a surface; lithographing the passivation layer so that the passivation layer will remain on the surface where the first island regions and the second island regions are provided; etching the surface of the semiconductor wafer with regard to the lithographed regions, so that a thickness of the semiconductor wafer is reduced perpendicularly to the lithographed regions of the surface so as to structure the surface region and to thus specify positions for the first island regions and the second island regions; and completely removing the passivation layer. 12. The method as claimed in claim 10 , wherein said arranging and connecting of the cover substrate comprises: connecting, region by region, the structured surface region of the mold substrate to a surface region of the carrier substrate, the mold substrate and the carrier substrate comprising a semiconductor material. 13. The method as claimed in claim 10 , wherein said arranging of the window component in each case comprises: providing several strip-shaped window components; and inserting the strip-shaped window components into the recesses located between the first island regions and the second island regions, so that surfaces of the window component

Assignees

Inventors

Classifications

  • between stacked chips · CPC title

  • changes in dispositions · CPC title

  • Die-attach connectors and bond wires · CPC title

  • Dispositions of multiple bond wires · CPC title

  • Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30 (H01S5/50 takes precedence) · CPC title

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What does patent US9912115B2 cover?
The invention relates to methods of producing a cap substrate, to methods of producing a packaged radiation-emitting device at the wafer level, and to a radiation-emitting device. By producing a cap substrate, providing a device substrate in the form of a wafer including a multitude of radiation-emitting devices, arranging the substrates one above the other such that the substrates are bonded a…
Who is the assignee on this patent?
Fraunhofer Ges Forschung
What technology area does this patent fall under?
Primary CPC classification H01S5/02208. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 06 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).