Solid-state imaging element, method for manufacturing solid-state imaging element, and electronic device

US9911870B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9911870-B2
Application numberUS-201414277391-A
CountryUS
Kind codeB2
Filing dateMay 14, 2014
Priority dateJan 25, 2011
Publication dateMar 6, 2018
Grant dateMar 6, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A solid-state imaging element including: a sensor substrate in which a photoelectric conversion section is arranged and formed; a circuit substrate in which a circuit for driving the photoelectric conversion section is formed, the circuit substrate being laminated to the sensor substrate; a sensor side electrode drawn out to a surface of the sensor substrate on a side of the circuit substrate and formed as one of a projection electrode and a depression electrode; and a circuit side electrode drawn out to a surface of the circuit substrate on a side of the sensor substrate, formed as one of the depression electrode and the projection electrode, and joined to the sensor side electrode in a state of the circuit side electrode and the sensor side electrode being fitted together.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a first substrate; a second substrate laminated to the first substrate; a projection electrode extending to a first surface of the first substrate which faces the second substrate, wherein the projection electrode includes a projecting surface that projects from the first surface of the first substrate; and a depression electrode extending to a second surface of the second substrate which faces the first substrate and joined to the projection electrode in a state of the projection electrode and the depression electrode being fitted together such that the projecting surface and a side surface of the projection electrode is in physical and electrical contact with a recessed surface and a side surface of the depression electrode, and the first surface of the first substrate and the second surface of the second substrate being in direct physical contact with one another, wherein the recessed surface of the depression electrode recedes from the second surface of the second substrate, wherein the projection electrode has a first width at the first surface of the first substrate, the depression electrode has a second width at the second surface of the second substrate, and the second width is greater than the first width. 2. The semiconductor device according to claim 1 , wherein a joining surface between the first electrode and the second electrode is a curved surface. 3. The semiconductor device according to claim 1 , wherein the projecting surface and the side surface of the projection electrode define an outer circumference that is surrounded by the depression electrode. 4. The semiconductor device according to claim 1 , further comprising: a first insulating film surrounding the projection electrode; and a second insulating film surrounding the depression electrode, wherein the first insulating film and the second insulating film are in close contact with each other. 5. The semiconductor device according to claim 1 , wherein the projecting surface of the projection electrode fits into the recessed surface of the depression electrode. 6. The semiconductor device according to claim 1 , wherein the projecting surface of the projection electrode comprises a plurality of projection parts; and the recessed surface of the depression electrode comprises a plurality of depression parts. 7. The semiconductor device according to claim 1 , wherein a peripheral surface of the depression electrode is flush with the second surface of the second substrate and in direct physical contact with the first surface of the first substrate. 8. The semiconductor device according to claim 1 , wherein the first substrate further includes a third surface opposite the first surface; and the projection electrode originates at a position between the first surface and the third surface of the first substrate. 9. A method of manufacturing a semiconductor device, comprising: providing a first substrate; providing a second substrate; forming a projection electrode in a first surface of the first substrate which faces the second substrate, wherein the projection electrode includes a projecting surface that projects from the first surface of the first substrate; forming a depression electrode in a second surface of the second substrate which faces the first substrate, wherein the depression electrode includes a recessed surface that recedes from the second surface of the second substrate; and laminating the second substrate to the first substrate such that the depression electrode is joined to the projection electrode in a state of the projection electrode and the depression electrode being fitted together such that the projecting surface and a side surface of the projection electrode is in physical and electrical contact with the recessed surface and a side surface of the depression electrode, and the first surface of the first substrate and the second surface of the second substrate being in direct physical contact with one another, wherein the projection electrode has a first width at the first surface of the first substrate, the depression electrode has a second width at the second surface of the second substrate, and the second width is greater than the first width. 10. The method according to claim 9 , wherein, in the step of laminating, a joining surface between the first electrode and the second electrode is a curved surface. 11. The method according to claim 10 , wherein in the step of forming the projection electrode, the projecting surface of the projection electrode comprises a plurality of projection parts; and in the step of forming the depression electrode, the recessed surface of the depression electrode comprises a plurality of depression parts. 12. The method according to claim 9 , wherein the projecting surface and the side surface of the projection electrode define an outer circumference and, in the step of laminating, the outer circumference is surrounded by the depression electrode. 13. The method according to claim 9 , further comprising: forming a first insulating film surrounding the projection electrode; and forming a second insulating film surrounding the depression electrode; wherein, in the step of laminating, the first insulating film and the second insulating film are in close contact with each other. 14. The method according to claim 9 , wherein, in the step of laminating, the projecting surface of the projection electrode fits into the recessed surface of the depression electrode. 15. An electronic apparatus comprising: a semiconductor device including: a first substrate; a second substrate laminated to the first substrate; a projection electrode extending to a first surface of the first substrate which faces the second substrate, wherein the projection electrode includes a projecting surface that projects from the first surface of the first substrate; and a depression electrode extending to a second surface of the second substrate which faces the first substrate and joined to the projection electrode in a state of the projection electrode and the depression electrode being fitted together such that the projecting surface and a side surface of the projection electrode is in physical and electrical contact with a recessed surface and a side surface of the depression electrode, and the first surface of the first substrate and the second surface of the second substrate being in direct physical contact with one another, wherein the recessed surface of the depression electrode recedes from the second surface of the second substrate, wherein the projection electrode has a first width at the first surface of the first substrate, the depression electrode has a second width at the second surface of the second substrate, and the second width is greater than the first width. 16. The electronic apparatus according to claim 15 , wherein a joining surface between the first electrode and the second electrode is a curved surface. 17. The electronic apparatus according to claim 15 , wherein the projecting surface and the side surface of the projection electrode define an outer circumference that is surrounded by the depression electrode. 18. The electronic apparatus according to claim 15 , further comprising: a first insulating film surrounding the projection electrode; and a second insulating film surrounding the depression electrode, wherein the first insulating film and the second insulating film are in close contact with each other. 19. The electronic appar

Assignees

Inventors

Classifications

  • characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

  • characterised by the direct bonding of electrically conductive pads · CPC title

  • comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

  • Bond pads having multiple stacked layers · CPC title

  • Structures or relative sizes of bond pads · CPC title

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What does patent US9911870B2 cover?
A solid-state imaging element including: a sensor substrate in which a photoelectric conversion section is arranged and formed; a circuit substrate in which a circuit for driving the photoelectric conversion section is formed, the circuit substrate being laminated to the sensor substrate; a sensor side electrode drawn out to a surface of the sensor substrate on a side of the circuit substrate a…
Who is the assignee on this patent?
Sony Corp
What technology area does this patent fall under?
Primary CPC classification H10F39/018. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 06 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).