Semiconductor device

Patent metadata

Field	Value
Publication number	US-9911856-B2
Application number	US-90014510-A
Country	US
Kind code	B2
Filing date	Oct 7, 2010
Priority date	Oct 9, 2009
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

One of objects is to provide a semiconductor device with stable electric characteristics, in which an oxide semiconductor is used. The semiconductor device includes a thin film transistor including an oxide semiconductor layer, and a silicon oxide layer over the thin film transistor. The thin film transistor includes a gate electrode layer, a gate insulating layer whose thickness is equal to or larger than 100 nm and equal to or smaller than 350 nm, the oxide semiconductor layer, a source electrode layer and a drain electrode layer. In the thin film transistor, the difference of the threshold voltage value is 1 V or less between before and after performance of a measurement in which the voltage of 30 V or −30 V is applied to the gate electrode layer at a temperature of 85° C. for 12 hours.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a transistor, the transistor comprising:
a gate electrode layer;
a gate insulating layer with a thickness equal to or larger than 100 nm and equal to or smaller than 350 nm;
an oxide semiconductor layer comprising indium, gallium, and zinc over the gate insulating layer;
a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer;
a silicon oxide layer over the source electrode layer and the drain electrode layer, the silicon oxide layer being in contact with the oxide semiconductor layer;
a mixed region between the oxide semiconductor layer and the silicon oxide; and
a protective insulating layer comprising nitrogen over and in contact with the silicon oxide layer,

wherein the mixed region comprises oxygen, silicon, and at least one of indium, gallium, and zinc,
wherein a thickness of the mixed region is from 1 nm to 10 nm, and
wherein a difference of a threshold voltage value of the transistor is 1 V or less, between before and after performance of a measurement in which a voltage of 30 V or −30 V is applied to the gate electrode layer at a temperature of 85° C. for 12 hours.

2. The semiconductor device according to claim 1 , wherein the source electrode layer comprises an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W.

3. The semiconductor device according to claim 1 , wherein a thickness of the mixed region is from 2 nm to 5 nm.

4. The semiconductor device according to claim 1 , wherein the mixed region comprises a metal element M existing in a state any of M-OH, M-H, M-O—Si—H, and M-O—Si—OH.

5. A semiconductor device comprising:
a transistor, the transistor comprising:
a gate electrode layer;
a gate insulating layer with a thickness equal to or larger than 100 nm and equal to or smaller than 350 nm;
an oxide semiconductor layer comprising indium, gallium, and zinc over the gate insulating layer;
a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; and
a silicon oxide layer over and in contact with the oxide semiconductor layer,

wherein a mixed region is placed at an interface between the oxide semiconductor layer and the silicon oxide,
wherein a hydrogen concentration in the interface is 5×10 19 /cm 3 or lower,
wherein the mixed region comprises oxygen, silicon, and at least one of indium, gallium, and zinc,
wherein a thickness of the mixed region is from 1 nm to 10 nm, and
wherein a difference of a threshold voltage value of the transistor is 1 V or less, between before and after performance of a measurement in which a voltage of 30 V or −30 V is applied to the gate electrode layer at a temperature of 85° C. for 12 hours.

6. The semiconductor device according to claim 5 , wherein the source electrode layer comprises an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W.

7. The semiconductor device according to claim 5 , wherein a thickness of the mixed region is from 2 nm to 5 nm.

8. The semiconductor device according to claim 5 , wherein the mixed region comprises a metal element M existing in a state any of M-OH, M-H, M-O—Si—H, and M-O—Si—OH.

Assignees

• Yamazaki Shunpei
• Miyanaga Akiharu
• Takahashi Masahiro
• Kishida Hideyuki
• Sakata Junichiro
• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Miyanaga Akiharu
• Takahashi Masahiro
• Kishida Hideyuki
• Sakata Junichiro

Classifications

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H01L29/78606

  Electricity · mapped topic

• H01L29/42384

  Electricity · mapped topic

• H01L29/7869 Primary

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic