Semiconductor memory devices having increased distance between gate electrodes and epitaxial patterns and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-9379134-B2
Application number	US-201514875840-A
Country	US
Kind code	B2
Filing date	Oct 6, 2015
Priority date	Nov 3, 2014
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

A semiconductor memory device is provided including a substrate, a plurality of interlayer insulating layers and gate electrodes alternately stacked on the substrate. The plurality of interlayer insulating layers and the gate electrodes define a channel hole that vertically penetrates the plurality of interlayer insulating layers and the gate electrodes to expose at least a portion of the substrate. A channel recess is provided in the substrate exposed by the channel hole. An epitaxial pattern fills the channel recess. The epitaxial pattern has an upper surface that is concave and curves inward in a middle portion thereof.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a substrate;
a plurality of interlayer insulating layers and gate electrodes alternately stacked on the substrate, the plurality of interlayer insulating layers and the gate electrodes defining a channel hole that vertically penetrates the plurality of interlayer insulating layers and the gate electrodes to expose at least a portion of the substrate;
a channel recess in the substrate exposed by the channel hole; and
an epitaxial pattern filling the channel recess, wherein the epitaxial pattern has an upper surface that is concave and curves inward in a middle portion thereof.

2. The device of claim 1 , wherein the upper surface of the epitaxial pattern includes an edge in contact with a sidewall of the channel recess, wherein the edge is positioned at a level substantially equivalent to an upper surface of the substrate.

3. The device of claim 1 , wherein the epitaxial pattern includes a same material as the substrate.

4. The device of claim 1 , wherein the epitaxial pattern is doped with impurities of a same conductivity type as the substrate.

5. The device of claim 1 , further comprising a vertical channel pattern disposed in the channel hole, wherein the vertical channel pattern is electrically connected to the epitaxial pattern.

6. The device of claim 5 , wherein the vertical channel pattern directly contacts the epitaxial pattern.

7. The device of claim 5 , wherein a bottom surface of the vertical channel pattern is positioned at a lower level than an upper surface of the substrate.

8. The device of claim 5 , further comprising a gate dielectric pattern surrounding an outside sidewall of the vertical channel pattern.

9. The device of claim 8 , wherein the gate dielectric pattern has a pipe shape.

10. The device of claim 8 , wherein the gate dielectric pattern includes a blocking insulating pattern, a charge trap pattern and a tunnel insulating pattern.

11. The device of claim 8 , wherein a bottom surface of the gate dielectric pattern is positioned at a level between an upper surface of the substrate and a bottom surface of the vertical channel pattern, wherein the upper surface of the substrate is positioned at a higher level than the bottom surface of the vertical channel pattern.

12. The device of claim 5 , further comprising a filling insulating pattern filling an inner space of the vertical channel pattern.

13. The device of claim 12 , further comprising a horizontal boundary between the filling insulating pattern and the vertical channel pattern and is positioned at a lower level than an upper surface of the substrate.

14. A semiconductor memory device, comprising:
a substrate including an epitaxial pattern;
a plurality of gate electrodes vertically stacked on the substrate;
a vertical channel pattern penetrating the plurality of gate electrodes and electrically connected to the epitaxial pattern; and
a gate dielectric pattern between the vertical channel pattern and the gate electrodes and surrounding a sidewall of the vertical channel pattern,
wherein the epitaxial pattern has a upper surface having a center portion that is positioned at a lower level than an edge thereof;
wherein the gate dielectric pattern has a bottom surface between the edge of the epitaxial pattern and the vertical channel pattern; and
wherein the bottom surface of the gate dielectric pattern is positioned at a lower level than a upper surface of the substrate.

15. The device of claim 14 , wherein the epitaxial pattern includes a same material as the substrate.

16. The device of claim 14 , wherein the epitaxial pattern is doped with impurities of a same conductivity type as the substrate.

17. The device of claim 14 , wherein the gate dielectric pattern includes a blocking insulating pattern, a charge trap pattern and a tunnel insulating pattern.

18. The device of claim 14 , wherein the gate dielectric pattern has a pipe shape.

19. The device of claim 14 , wherein the bottom surface of gate dielectric pattern is positioned at a higher level than a bottom surface of the vertical channel pattern.

20. A semiconductor memory device, comprising:
a plurality of gate electrodes vertically stacked on the substrate;
a vertical channel pattern penetrating the gate electrodes and electrically connected to an epitaxial pattern; and
a filling insulating pattern filling an inner space of the vertical channel pattern,
wherein a horizontal boundary between the vertical channel pattern and the filling insulating pattern is positioned at a lower level than the upper surface of the substrate.

Assignees

• Lee Joonsuk
• Lee Woosung
• Lee Woong
• Samsung Electronics Co Ltd

Inventors

• Lee Joonsuk
• Lee Woosung
• Lee Woong

Classifications

• H01L27/11582 Primary

  Electricity · mapped topic

• H10B41/30 Primary

  characterised by the memory core region · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title