Through-body-via isolated coaxial capacitor and techniques for forming same

Patent metadata

Field	Value
Publication number	US-9911689-B2
Application number	US-201315038623-A
Country	US
Kind code	B2
Filing date	Dec 23, 2013
Priority date	Dec 23, 2013
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor provided using the disclosed techniques may include, for example, a conductive TBV surrounded by a dielectric material and an outer conductor plate. The TBV and outer plate can be formed, for example, so as to be self-aligned with one another in a coaxial arrangement, in accordance with some embodiments. The disclosed capacitor may extend through the body of a host die such that its terminals are accessible on the upper and/or lower surfaces thereof. Thus, in some cases, the host die can be electrically connected with another die to provide a die stack or other three-dimensional integrated circuit (3D IC), in accordance with some embodiments. In some instances, the disclosed capacitor can be utilized, for example, to provide integrated capacitance in a switched-capacitor voltage regulator (SCVR).

First claim

What is claimed is:

1. A method of forming an integrated circuit, the method comprising:
forming an electrically conductive plate within a trench in a semiconductor layer, the trench surrounding a portion of the semiconductor layer, such that the plate surrounds the portion of the semiconductor layer after the plate is formed;
removing the portion of the semiconductor layer to form an additional trench;
forming a dielectric layer in the additional trench and within an interior region bounded by the plate; and
forming an electrically conductive through-body via (TBV) in the additional trench and within an interior region bounded by the dielectric layer, wherein the TBV and plate are arranged coaxially, and wherein the dielectric layer electronically isolates the TBV and plate.

2. The method of claim 1 further comprising:
forming a front-end transistor layer over the semiconductor layer.

3. The method of claim 1 further comprising at least one of:
forming a back-end layer over the semiconductor layer, plate, dielectric layer, and TBV, wherein the back-end layer is in electronic contact with at least one of the plate and/or TBV; and
bonding a carrier substrate to the back-end layer.

4. The method of claim 1 , wherein the trench in the semiconductor layer is formed using a first etch into which the conductive plate is deposited, and a subsequent second etch completely removes the portion of the semiconductor layer that is surrounded by the plate the additional trench, the second etch being selective to the conductive plate, such that a location of the conductive TBV is self-aligned to a location of the conductive plate.

5. The method of claim 1 further comprising at least one of:
electronically connecting at least one of the plate and/or TBV with a redistribution layer (RDL); and
forming a surface finish layer over the RDL.

6. The method of claim 4 , further comprising forming a barrier layer prior to forming the dielectric layer, such that the barrier layer is between the dielectric layer and the conductive plate, wherein the barrier layer includes at least one of tantalum, titanium, and/or nitrogen.

7. The method of claim 1 , wherein forming the electrically conductive TBV includes an etch that is selective to the conductive plate, such that a location of the conductive TBV is self-aligned to a location of the conductive plate.

Assignees

• Intel Corp

Inventors

• Lee Kevin J
• Saraswat Ruchir
• Zillmann Uwe
• Cowley Nicholas P
• Schaefer Andre
• Jain Rinkle
• Droege Guido

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2128

  Coaxial through-semiconductor vias · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/635

  Through-vias · CPC title