Vector-matrix multiplications involving negative values

Patent metadata

Field	Value
Publication number	US-9910827-B2
Application number	US-201615201040-A
Country	US
Kind code	B2
Filing date	Jul 1, 2016
Priority date	Jul 1, 2016
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

Examples herein relate to circuits for computing vector-matrix multiplications involving negative values. A first memory crossbar array may be mapped to a first matrix which includes the positive values of an input matrix. A second memory crossbar array may be mapped to a second matrix which includes the negative values of the input matrix. An analog-to-digital converter may generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays. The digital intermediate multiplication results may include an intermediate result corresponding to a multiplication of each of the first vector and second vector with each of the first matrix and the second matrix. A controller may aggregate the digital intermediate results to generate a combined multiple result that represents the vector-matrix multiplication of the input vector and the input matrix.

First claim

What is claimed is:

1. A circuit, comprising:
a first memory crossbar array and a second memory crossbar array, each to compute analog multiplications, wherein the first memory crossbar array is mapped according to a first matrix comprising positive elements of an input matrix, and the second memory crossbar array is mapped according to a second matrix comprising negative elements of the input matrix;
an analog-to-digital converter (ADC) to generate digital intermediate multiplication results based on analog results computed by the memory crossbar arrays, wherein the digital intermediate multiplication results comprise a first intermediate result corresponding to a multiplication of the first matrix and a first vector comprising positive elements of an input vector, a second intermediate result corresponding to a multiplication of the second matrix and the first vector, a third intermediate result corresponding to a multiplication of the first matrix and a second vector comprising negative elements of the input vector, and a fourth intermediate result corresponding to a multiplication of the second matrix and the second vector; and
a controller to aggregate the digital intermediate results to generate a combined multiplication result.

2. The circuit of claim 1 , wherein the controller is to:
segregate the input matrix into the first matrix and the second matrix, wherein the first matrix comprises a copy of the input matrix with the negative elements of the input matrix set to zero in the first matrix, and wherein the second matrix comprises a copy of the input matrix with the positive elements of the input matrix set to zero in the second matrix; and
segregate the input vector into the first vector and the second vector, wherein the first vector comprises a copy of the input vector with the negative elements of the input vector set to zero in the first vector, and wherein the second vector comprises a copy of the input vector with the positive elements of the input vector set to zero in the second vector.

3. The circuit of claim 1 , further comprising a digital-to-analog converter (DAC) to generate a first set of input voltages corresponding to the first vector and a second set of input voltages corresponding to the second vector.

4. The circuit of claim 3 , wherein the controller is to:
deliver the first set of input voltages to the first memory crossbar array and the second memory crossbar array in parallel; and
deliver the second set of set of input voltages to the first memory crossbar array and the second memory crossbar array in parallel.

5. The circuit of claim 4 , wherein each of the first memory crossbar array and the second memory crossbar array comprises a plurality of row lines, a plurality of column lines, and a memory cell coupled between each unique combination of one row line and one column line, wherein:
the row lines of the first memory crossbar array and of the second memory crossbar array are to receive the first set of input voltages and the second set of input voltages; and
the column lines of the first memory crossbar array is to deliver a first set of output currents corresponding to the first intermediate result and a third set of output currents corresponding to the third intermediate result, and the column lines of the second memory crossbar array are to deliver a second set of outputs current corresponding to the second intermediate result and a fourth set of output currents corresponding to the fourth intermediate result.

6. The circuit of claim 1 , further comprising an iteration buffer to store the digital intermediate results prior to the controller aggregating the intermediate results to generate a combined multiplication result.

7. A hardware accelerator, comprising:
a first crossbar array and a second crossbar array each programmed to compute analog multiplications, wherein each crossbar array comprises a plurality of row lines, a plurality of column lines, and a memory cell coupled between each unique combination of one row line and one column line, wherein:
the memory cells of the first crossbar array are programmed according to positive elements of an input matrix, and the memory cells of the second crossbar array are programmed according to negative elements of the input matrix;
the row lines of the first crossbar array and of the second crossbar array are to receive a first set of input voltages corresponding to positive elements of an input vector and a second set of input voltages corresponding to negative elements of the input vector; and
the column lines of the first crossbar array are to deliver a first set of output currents from the first set of input voltages and a third set of output currents from the second set of input voltages, and the column lines of the second crossbar array are to deliver a second set of output currents from the first set of input voltages and a fourth set of output currents from the second set of input voltages;

an analog-to-digital converter (ADC) to generate a digital intermediate result corresponding to each set of output currents; and
a controller to aggregate the digital intermediate results to generate a combined multiplication result.

8. The hardware accelerator of claim 7 , wherein the controller is to:
segregate the input matrix into the first matrix and the second matrix, wherein the first matrix comprises the positive elements of the input matrix, and wherein the second matrix comprises the negative elements of the input matrix; and
segregate the input vector into the first vector and the second vector, wherein the second vector comprises the positive elements of the first vector, and wherein the third vector comprises the negative elements of the first vector.

9. The hardware accelerator of claim 8 , wherein:
the first matrix comprises a copy of the input matrix with the negative elements of the input matrix set to zero in the first matrix;
the second matrix comprises a copy of the input matrix with the positive elements of the input matrix set to zero in the second matrix;
the first vector comprises a copy of the input vector with the negative elements of the input vector set to zero in the first vector; and
the second vector comprises a copy of the input vector with the positive elements of the input vector set to zero in the second vector.

10. A circuit, comprising:
a memory crossbar array to compute analog multiplications, wherein the memory crossbar array is programmed according to an input matrix;
a digital-to analog converter (DAC) to generate a set of analog voltage values corresponding to an input vector;
an analog-to-digital converter (ADC) to generate a digital value for the analog multiplication results computed by the memory crossbar array;
a shifter to shift the digital value of a first analog multiplication result a predetermined number of bits to generate a shifted result, wherein the digital value of the first analog multiplication result corresponds to a multiplication of a first vector with the input matrix wherein the first vector comprises the most significant bits of elements of the input vector; and
an adder to add or subtract the shifted result to the digital value of a second multiplication result to generate a combined multiplication result, wherein the digital value of the second multiplication result corresponds to a multiplication of a second vector with the input matrix wherein the second vector comprises other bits of the elements of the input vector.

11. The circuit of claim 10 , wherein the most significant bits of the elements of the input vector indicate the sign of the elements of the input vector.

12. The circuit of claim 11 , whe

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Muralimanohar Naveen
• Feinberg Ben
• Shafiee Ardestani Ali

Classifications

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• G06F7/4876 Primary

  Multiplying · CPC title

• G06G7/16 Primary

  for multiplication or division {(G06G7/19 and G06G7/24 take precedence; measuring electric power G01R21/00)} · CPC title