Printed circuit board and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9907164-B2
Application number	US-201113997569-A
Country	US
Kind code	B2
Filing date	Dec 23, 2011
Priority date	Dec 24, 2010
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

Disclosed are a printed circuit board and a method for manufacturing the same. The printed circuit board includes a core insulating layer, at least one via formed through the core insulating layer, an inner circuit layer buried in the core insulating layer, and an outer circuit layer on a top surface or a bottom surface of the core insulating layer. The via includes a first part, a second part below the first part, and a third part between the first and second parts, and the third part includes a metal different from a metal of the first and second parts. The inner circuit layer and the via are simultaneously formed.

First claim

The invention claimed is:

1. A printed circuit board comprising:
a first insulating layer;
a second insulating layer disposed below the first insulating layer;
a via formed through the first and second insulating layers;
an inner circuit layer buried in the first and second insulating layers; and
an outer circuit layer on a top surface of the first insulating layer or a bottom surface of the second insulating layer;
wherein the via includes a first part, a second part below the first part, and a third part between the first and second parts, and the third part includes a metal different from a metal of the first and second parts;
wherein the inner circuit layer comprises:
a first portion buried in a lower part of the first insulating layer, and
a second portion buried in an upper part of the second insulating layer and directly contacted with the first portion;
wherein the inner circuit layer is spaced apart from the via in a horizontal direction;
wherein a sectional shape of the third part of the via is the same as a sectional shape of the first portion of the inner circuit layer,
wherein a top surface of the third part of the via lies in a same plane as a top surface of the first portion of the inner circuit layer,
wherein a bottom surface of the third part of the via lies in a same plane as a bottom surface of the first portion of the inner circuit layer,
wherein the first and second parts of the via are formed by using a same material,
wherein the first portion of the inner circuit layer and the third part of the via are formed by using a same material,
wherein a bottom surface of the first part is directly contacted with a top surface of the third part, and a bottom surface of the third part is directly contacted with a top surface of the second part;
wherein a combined sectional shape of the first part, the second part, and the third part is hexagonal; and
wherein a combined sectional shame of the first portion and the second portion is hexagonal.

2. The printed circuit board of claim 1 , wherein the first and second parts of the via are formed by using a same material.

3. The printed circuit board of claim 1 , wherein the first portion of the inner circuit layer is symmetrical to the second portion of the inner circuit layer about a boundary between the first insulating layer and the second insulating layer.

4. The printed circuit board of claim 1 , wherein the printed circuit board comprises a circuit layer including the inner circuit layer and the outer circuit layer and having a number of 2n+1 (n is a positive integer).

5. The printed circuit board of claim 1 , wherein the outer circuit layer is filled in a pattern groove formed in the top surface of the first insulating layer or the bottom surface of the second insulating layer.

6. The printed circuit board of claim 5 , wherein the pattern groove has a U-sectional shape.

7. A method for manufacturing a printed circuit board, the method comprising:
preparing a metal substrate having a stack structure including a first metal layer, a second metal layer, and a third metal layer;
forming a first part of a via by etching the first metal layer of the metal substrate;
simultaneously forming a connecting part of the via and a first portion of an inner circuit layer by etching the second metal layer of the metal substrate;
simultaneously forming a second part of the via under the connecting part and a second portion of the inner circuit layer under the first portion by etching the third metal layer of the metal substrate;
forming a first insulating layer to bury the first part of the via, the connecting part, and the first portion of the inner circuit layer;
forming a second insulating layer to bury the second part of the via and the second portion of the inner circuit layer; and
forming an outer circuit layer on a top surface of the first insulating layer or a bottom surface of the second insulating layer;
wherein the inner circuit layer is spaced apart from the via in a horizontal direction;
wherein a sectional shape of the connecting part of the via is same as a sectional shape of the first portion of the inner circuit layer,
wherein a top surface of the connecting part of the via lies in a same plane as a top surface of the first portion of the inner circuit layer,
wherein a bottom surface of the connecting part of the via lies in a same plane as a bottom surface of the first portion of the inner circuit layer,
wherein the first and second parts of the via are formed by using a same material,
wherein the first inn, layer and the connecting part of the via are, formed by using a same material,
wherein a bottom surface of the first part is directly contacted with a top surface of the connecting part, and a bottom surface of the connecting part is directly contacted with a top surface of the second part;
wherein a combined sectional shape of the first part, the second part, and the connection part is hexagonal; and
wherein a combined sectional shape of the first portion and the second portion is hexagonal.

8. The method of claim 7 , wherein the forming of the outer circuit layer comprises:
forming a copper foil layer on the first insulating layer and under the second insulating layer;
forming a photoresist pattern on the copper foil layer; and
forming the outer circuit layer by etching the copper foil layer using the photoresist pattern as a mask.

9. The method of claim 7 , wherein a width of a boundary between the second and connecting parts of the via is larger than a width of a top surface of the first part or a bottom surface of the second part.

10. The method of claim 7 , wherein the first portion of the inner circuit layer is symmetrical to the second portion of the inner circuit layer about a boundary between the first insulating layer and the second insulating layer.

11. The method of claim 7 , wherein the forming of the outer circuit layer comprises:
forming a pattern groove on the top surface of the first insulating layer or the bottom surface of the second insulating layer; and
forming the outer circuit layer by plating a conductive material to fill the pattern groove.

Assignees

• Lee Sang Myung
• Yoon Sung Woon
• Lee Hyuk Soo
• Lee Sung Won
• Chun Ki Do
• Lg Innotek Co Ltd

Inventors

• Lee Sang Myung
• Yoon Sung Woon
• Lee Hyuk Soo
• Lee Sung Won
• Chun Ki Do

Classifications

• H05K3/4652

  Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern (H05K3/4647 takes precedence) · CPC title

• H05K3/4682 Primary

  Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil · CPC title

• H05K2201/0338

  Layered conductor, e.g. layered metal substrate, layered finish layer or layered thin film adhesion layer · CPC title

• H05K2203/0376

  Etching temporary metallic carrier substrate · CPC title

• H05K3/4647

  by applying an insulating layer around previously made via studs · CPC title