Cross-talk reduction for high speed signaling at ball grid array region and connector region

Patent metadata

Field	Value
Publication number	US-9907156-B1
Application number	US-201514640801-A
Country	US
Kind code	B1
Filing date	Mar 6, 2015
Priority date	Mar 6, 2015
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A multilayered printed circuit board (PCB) may include a plurality of pads associated with facilitating a connection to a component. The component may include a first edge and a second edge. The plurality of pads may include a first pad, located between a second pad and the first edge. The PCB may include a plurality of vertically disposed vias electrically connected to the plurality of pads and a plurality of horizontally disposed signal layers, electrically connected by the plurality of vias, to route a set of signals toward the first edge. The set of signals may include a first signal that is routed by a first via, of the plurality of vias, and a first signal layer of the plurality of signal layers and a second signal that is routed by a second via, of the plurality of vias, and a second signal layer of the plurality of signal layers.

First claim

What is claimed is:

1. A multilayered printed circuit board (PCB) comprising:
a plurality of pads associated with facilitating a connection to a component,
the component having a first edge and a second edge,
the plurality of pads including a first pad and a second pad,
the first pad being located between the second pad and the first edge;

a plurality of vertically disposed vias electrically connected to the plurality of pads; and
a plurality of horizontally disposed signal layers, electrically connected by the plurality of vertically disposed vias, to route a set of signals toward the first edge,
the plurality of horizontally disposed signal layers including a transmitter signal routing layer and a receiver signal routing layer, and
the set of signals including:
a first signal that is routed by a first via, of the plurality of vertically disposed vias, and the transmitter signal routing layer,
the first via being associated with the first pad, and

a second signal that is routed by a second via, of the plurality of vertically disposed vias, and the receiver signal routing layer,
the second via being associated with the second pad,
the transmitter signal routing layer being located closer to a top surface of the PCB than the receiver signal routing layer, and
the first via being selectively backdrilled between the transmitter signal routing layer and the receiver signal routing layer based on the set of signals being routed toward the first edge,
 the second via not being backdrilled based on the first via being selectively backdrilled.

2. The multilayered PCB of claim 1 , further comprising:
one or more ground layers located between the transmitter signal routing layer and the receiver signal routing layer.

3. The multilayered PCB of claim 1 , where the component connects to the PCB using a ball grid array.

4. The multilayered PCB of claim 1 , where the PCB is associated with a serializer/deserializer (SerDes) application specific integrated circuit (ASIC).

5. The multilayered PCB of claim 1 , where the PCB is connected to the component,
the component being associated with facilitating a high speed serial link.

6. The multilayered PCB of claim 1 , where backdrilling the first via removes a via stub from the PCB at a location within the PCB between the transmitter signal routing layer and the receiver signal routing layer.

7. The multilayered PCB of claim 1 , where the plurality of vertically disposed vias are arranged in a ball grid array; and
where the first via and the second via are located in the ball grid array as an interleaved pair.

8. The multilayered PCB of claim 1 , where the plurality of vertically disposed vias are arranged in a ball grid array;
where the first via is located in the ball grid array as an adjacent pair with a third via of the plurality of vertically disposed vias; and
where the second via is located in the ball grid array as another adjacent pair with a fourth via of the plurality of vertically disposed vias.

9. A device comprising:
a plurality of pads to connect an integrated circuit to the device via a ball grid array,
the plurality of pads being located on a top surface of the device;

a plurality of vertically disposed vias connected to one or more pads of the plurality of pads; and
a plurality of signal layers, electrically connected by the plurality of vertically disposed vias, to route a plurality of signals to and from the integrated circuit,
the plurality of signal layers including a transmitter signal routing layer and a receiver signal routing layer, and
the plurality of signals including:
a first signal that is routed by a first via of the plurality of vertically disposed vias, a first pad of the plurality of pads, and the receiver signal routing layer,
the first via being associated with the first pad, and

a second signal that is routed by a second via of the plurality of vertically disposed vias, a second pad of the plurality of pads, and the transmitter signal routing layer,
the receiver signal routing layer being positioned within the device based on a direction of signal routing at the receiver signal routing layer,
the transmitter signal routing layer being positioned within the device based on a direction of signal routing at the transmitter signal routing layer, and
the first via being selectively backdrilled to a location within the device between the receiver signal routing layer and the transmitter signal routing layer based on the plurality of signals being routed toward a particular edge of the device, a position of the first pad in the ball grid array, and a position of the second pad in the ball grid array,
 the second via not being backdrilled based on the first via being selectively backdrilled.

10. The device of claim 9 , further comprising:
one or more ground layers located between the receiver signal routing layer and the transmitter signal routing layer.

11. The device of claim 9 , where the first via and the second via are adjacent vias.

12. The device of claim 9 , where the direction of signal routing at the receiver signal routing layer is from an inner portion of the ball grid array toward an outer portion of the ball grid array;
where the first via being located between the second via and the outer portion of the ball grid array,
the first via being an outer via,

where the receiver signal routing layer is positioned between the top surface of the device and the transmitter signal routing layer based on the direction of signal routing at the receiver signal routing layer being from the inner portion of the ball grid array toward the outer portion of the ball grid array and based on the first via being the outer via; and
where the first via is backdrilled based on the direction of signal routing at the receiver signal routing layer being from the inner portion of the ball grid array toward the outer portion of the ball grid array and based on the first via being the outer via.

13. The device of claim 9 , where the direction of signal routing at the receiver signal routing layer is from an outer portion of the ball grid array toward an inner portion of the ball grid array;
where the first via is located between the second via and the inner portion of the ball grid array,
the first via being an inner via,

where the receiver signal routing layer is positioned between the top surface of the device and the transmitter signal routing layer based on the direction of signal routing at the receiver signal routing layer being from the outer portion of the ball grid array toward the inner portion of the ball grid array and based on the first via being the inner via; and
where the first via is backdrilled based on the direction of signal routing at the receiver signal routing layer being from the outer portion of the ball grid array toward the inner portion of the ball grid array and based on the first via being the inner via.

14. The device of claim 9 , where the integrated circuit is associated with a serializer/deserializer (SerDes) application-specific integrated circuit (ASIC).

15. A method, comprising:
fabricating, by a device, a printed circuit board (PCB) to include:
a plurality of vertically disposed vias, and
a plurality of horizontally disposed signal layers, electrically connected by the plurality of vertically disposed vias, to route signals to or from a via of the plurality of vertically disposed vias,
the plurality of horizontally disposed signal layers including:
a first signal layer electrically connected to a first via, of the plurality of vertically disposed vias, and a

Assignees

• Juniper Networks Inc

Inventors

• Anand Raja C T
• Brugumalla Satish Kumar

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/635

  Through-vias · CPC title

• H05K1/0216 Primary

  Reduction of cross-talk, noise or electromagnetic interference (grounding H05K1/0215) · CPC title

• H05K1/113

  Via provided in pad; Pad over filled via · CPC title