Digital-to-analog converter and method of operating

Patent metadata

Field	Value
Publication number	US-9906237-B1
Application number	US-201715582355-A
Country	US
Kind code	B1
Filing date	Apr 28, 2017
Priority date	Apr 28, 2017
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A digital-to-analog converter includes an adder having a plurality of inputs and an output coupled to the output of the converter. The converter further includes a plurality of digital-to-analog (DAC) elements, each DAC element has an output coupled to an input of the adder, and each DAC element has a DAC element input. A plurality of comparators have outputs coupled to a DAC element input. A first input of each comparator is coupled to the input of the converter. A second input of each comparator is selectively coupled to one of a predetermined voltage and a pseudo-random bit sequence (PRBS[n]).

First claim

What is claimed is:

1. A digital-to-analog converter comprising:
an adder having a plurality of inputs and an output, the output of the adder being coupled to the output of the converter;
a plurality of digital-to-analog (DAC) elements, each DAC element having an output coupled to an input of the adder, and each DAC element having a DAC element input; and
a plurality of comparators, the output of each comparator coupled to a single DAC element input, a first input of each comparator coupled to the input of the converter, a second input of each comparator selectively coupled to one of a predetermined voltage input and a pseudo-random bit sequence (PRBS[n]) input.

2. The converter of claim 1 , further comprising a processor operable to select which of the plurality of comparator second inputs is selectively coupled to the predetermined voltage input or to the PRBS[n] input.

3. The converter of claim 2 , wherein the processor is operable to a couple a second input of one of the plurality of comparators to the PRBS[n] input while decoupling the second input of the one comparator from the predetermined voltage input.

4. The converter of claim 2 , wherein the processor is operable to selectively couple a second input of a first comparator to the PRBS[n] input and concurrently selectively couple a second input of a second comparator to the complement of the PRBS[n] input.

5. The converter of claim 1 , further comprising a resistive network having a plurality of nodes, each node providing a predetermined voltage selectively coupled to each of the second inputs of the plurality of comparators.

6. The converter of claim 5 , further comprising a plurality of switches, each switch coupled in parallel with individual resistors in the resistive network, wherein the individual switches are operable to shunt individual resistors coupled to second inputs of comparators.

7. The converter of claim 1 , further comprising a resistive network operable to provide the plurality of predetermined voltages, wherein the second input of each comparator is selectively coupled to: at least one predetermined voltage of the resistive network, the PRBS[n] input, or the complement of the PRBS[n] input.

8. The converter of claim 7 , further comprising a plurality of switches, each switch coupled in parallel with individual resistors in the resistive network, wherein the individual switches are operable to shunt individual resistors coupled to second inputs of comparators having second inputs coupled to the PRBS[n] input or the complement of the PRBS[n] input.

9. A delta-sigma modulator comprising:
a loop filter having a filter input and a filter output;
a digital signal generator operable to generate a digital signal;
a digital-to-analog converter (DAC) comprising:
a digital input coupled to the filter output;
an analog output coupled to the filter input;
a plurality of comparators, each comparator having a first input coupled to the digital input and each comparator having a second input selectively coupled to one of the digital signal and a predetermined voltage;
a plurality of DAC elements, the input of each DAC element coupled to an output of one of the plurality of comparators and the outputs of the plurality of DAC elements coupled to the analog output; and

a corrector coupled to the filter output, the corrector operable to apply a correction coefficient to the filter output; and
an estimator coupled to the corrector and the digital signal generator, the estimator operable to generate the correction coefficient in response to a comparator being coupled to the digital signal and decoupled from the predetermined voltage.

10. The modulator of claim 9 , further comprising a decimation filter coupled between the corrector and the estimator.

11. The modulator of claim 9 , wherein the digital signal generator is a pseudo random bit sequence generator and the digital signal is a pseudo random bit sequence.

12. The modulator of claim 9 , wherein the correction coefficient compensates for errors caused by at least one DAC element.

13. The modulator of claim 12 , wherein the correction coefficient compensates for static errors in at least one DAC element.

14. The modulator of claim 12 , wherein the correction coefficient compensates for dynamic errors in at least one DAC element.

15. The modulator of claim 9 , further comprising switches operable to selectively couple the second input of a first comparator to the digital signal and selectively couple the second input a second comparator to the complement of the digital signal, and wherein the estimator is operable to generate the correction coefficient in response to the output of a first DAC element coupled to the output of the first comparator and the output of a second DAC element coupled to the output of the second comparator.

16. A method of calibrating a delta-sigma modulator having a delta sigma filter and a feedback digital-to-analog converter (DAC) having a plurality of DAC elements, the method comprising:
decoupling a first DAC element from an input of the DAC;
coupling the first DAC element to a digital signal;
converting the digital signal to an analog signal using the first DAC element;
analyzing the output of the delta-sigma filter in response to the analog signal, the analyzing determining at least one error in the digital-to-analog conversion performed by the first DAC element; and
applying a correction coefficient to the output of the delta-sigma filter in response to the analysis of the output of the delta-sigma filter, the correction coefficient compensating for the at least one error in the output of the first DAC element.

17. The method of claim 16 , wherein the digital signal is a pseudo-random bit sequence.

18. The method of claim 16 , further comprising:
recoupling the first DAC element to the input of the DAC;
decoupling a second DAC element from an input of the DAC;
coupling the second DAC element to the digital signal;
converting the digital signal to an analog signal using the second DAC element; and
analyzing the output of the delta-sigma filter in response to the analog signal generated by the second DAC element, the analyzing determining at least one error in the digital-to-analog conversion performed by the second DAC element; and
wherein the applying further includes applying a correction coefficient to the output of the delta-sigma filter in response to the analyzing, the correction coefficient compensating for the at least one error generated by the second DAC element.

19. The method of claim 16 further comprising:
decoupling a second DAC element from an input of the DAC;
coupling the second DAC element to the complement of the digital signal;
converting the complement of the digital signal to an analog signal using the second DAC element;
adding the analog signal generated by the first DAC element to the analog signal generated by the second DAC element to generate a cumulative analog signal;
analyzing the output of the delta-sigma filter in response to the cumulative analog signal, the analyzing determining at least one error in the digital-to-analog conversion performed by the first DAC element and the second DAC element; and
wherein applying a correction coefficient includes applying a correction signal to the output of the delta-sigma filter in response the analysis of the output of the delta-sigma filter in response to the cumulative analog signal.

Assignees

• Texas Instruments Inc

Inventors

• Venkataraman Jagannathan
• Miglani Eeshan
• Gunasekaran Karthikeyan

Classifications

• H03M1/00

  Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/747

  with equal currents which are switched by unary decoded digital signals · CPC title

• H03M3/38 Primary

  Calibration · CPC title

• H03M3/50

  Digital/analogue converters using delta-sigma modulation as an intermediate step (digital delta-sigma modulators per se H03M7/3004) · CPC title