Biased impedance circuit, impedance adjustment circuit, and associated signal generator

Patent metadata

Field	Value
Publication number	US-9906209-B2
Application number	US-201715498525-A
Country	US
Kind code	B2
Filing date	Apr 27, 2017
Priority date	May 27, 2016
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A biased impedance circuit, an impedance adjustment circuit, and an associated signal generator are provided. The biased impedance circuit is coupled to a summation node and applies a biased impedance to the summation node. A periodic input signal is received at the summation node. The biased impedance circuit includes a switching circuit for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal. The switching circuit includes a low impedance path and a high impedance path. The low impedance sets the biased impedance to a first impedance when the output window signal is at a first voltage level. The high impedance path sets the biased impedance to a second impedance when the output window signal is at a second voltage level. The first impedance is less than the second impedance.

First claim

What is claimed is:

1. A biased impedance circuit coupled to a summation node, wherein the biased impedance circuit applies a biased impedance to the summation node, a periodic input signal is received at the summation node, and the biased impedance circuit comprises:
a switching circuit, for receiving an output window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal, wherein the switching circuit comprises:
a low impedance path, for setting the biased impedance to a first impedance when the output window signal is at a first voltage level, wherein a duration when the output window signal is at the first voltage level is corresponding to a significant transition of the periodic input signal; and
a high impedance path, for setting the biased impedance to a second impedance when the output window signal is at a second voltage level, wherein the first impedance is less than the second impedance.

2. The biased impedance circuit according to claim 1 , wherein the switching circuit conducts a direct current voltage to the summation node, and the periodic input signal and the direct current voltage are superimposed at the summation node.

3. The biased impedance circuit according to claim 2 , further comprising:
a bias circuit, coupled to a voltage source, a ground terminal and the switching circuit, wherein the bias circuit generates the direct current voltage.

4. The biased impedance setting circuit according to claim 2 , wherein the switching circuit is coupled to a first voltage source and a second voltage source, wherein the direct current voltage is between the first voltage source and the second voltage source.

5. The biased impedance circuit according to claim 1 , wherein the low impedance path comprises:
at least one switch, wherein the biased impedance is changed in response to a conducting status of the at least one switch, and the conducting status is controlled by the output window signal.

6. An impedance adjustment circuit, coupled to a summation node, wherein a periodic input signal is received at the summation node, and the impedance adjustment circuit applies a biased impedance to the summation node, wherein the impedance adjustment circuit comprises:
a window control circuit, for generating an output window signal according to at least one input window signal, wherein a period of the output window signal is shorter than a period of the periodic input signal, and a period of the at least one input window signal is shorter than or equivalent to the period of the periodic input signal; and
a biased impedance circuit, coupled to the window control circuit and the summation node, wherein the biased impedance circuit comprises a switching circuit, wherein the switching circuit receives the output window signal from the window control circuit, and the switching circuit comprises:
a low impedance path, for setting the biased impedance to a first impedance when the output window signal is at a first voltage level, wherein a duration when the output window signal is at the first voltage level is corresponding to a significant transition of the periodic input signal; and
a high impedance path, for setting the biased impedance to a second impedance when the output window signal is at a second voltage level, wherein the first impedance is less than the second impedance.

7. The impedance adjustment circuit according to claim 6 , wherein a duty cycle of the output window signal is less than or equivalent to 50%.

8. The impedance adjustment circuit according to claim 6 , wherein the switching circuit conducts a direct current voltage to the summation node, and the periodic input signal and the direct current voltage are superimposed at the summation node.

9. The impedance adjustment circuit according to claim 6 , wherein
the window control circuit is coupled to a squaring buffer, and the squaring buffer generates the at least one input signal according to the periodic input signal; or
the window control circuit is coupled to a reference clock circuit, and the reference clock circuit generates the at least one input window signal.

10. The impedance adjustment circuit according to claim 6 , wherein
the at least one input window signal and the periodic input signal are in phase, or
the at least one input window signal and the periodic input signal are out of phase.

11. The impedance adjustment circuit according to claim 6 , wherein the window control circuit comprises:
a delay circuit, for generating a first delay signal and a second delay signal; and
a window generator, coupled to the delay circuit, for generating the output window signal according to the first delay signal and the second delay signal.

12. The impedance adjustment circuit according to claim 11 , wherein the delay circuit shifts the input window signal and accordingly generates a shift window signal, wherein
the first delay signal and the second delay signal are generated based on the shift window signal, and a significant transition of the shift window signal is between a significant transition of the first delay signal and a significant transition of the second delay signal.

13. The impedance adjustment circuit according to claim 12 , wherein the window control circuit further comprises:
a calibration circuit, coupled to the delay circuit, for generating a calibration signal in response to a time difference between the input window signal and the shift window signal.

14. The impedance adjustment circuit according to claim 6 , wherein the low impedance path comprises:
at least one switch, wherein the biased impedance is changed in response to a conducting status of the at least one switch, and the conducting status is controlled by the output window signal.

15. A signal generator, comprising:
a periodic signal source, for transmitting a periodic input signal to a summation node;
an impedance adjustment circuit, coupled to the summation node, wherein the impedance adjustment circuit applies a biased impedance to the summation node, and the impedance adjustment circuit comprises:
a window control circuit, for generating an output window signal according to at least one input window signal; and
a biased impedance circuit, coupled to the window control circuit and the summation node, wherein the biased impedance circuit comprises a switching circuit, wherein the switching circuit receives the output window signal from the window control circuit, and the switching circuit comprises:
a low impedance path, for setting the biased impedance to a first impedance when the output window signal is at a first voltage level, wherein a duration when the output window signal is at the first voltage level is corresponding to a significant transition of the periodic input signal; and
a high impedance path, for setting the biased impedance to a second impedance when the output window signal is at a second voltage level, wherein the first impedance is less than the second impedance; and

a squaring buffer, coupled to the summation node, for generating an adjusted clock signal according to the periodic input signal and a direct current voltage,
wherein a period of the output window signal is shorter than a period of the at least one input window signal and a period of the periodic input signal,
the period of the periodic input window signal and a period of the adjusted clock signal are equivalent, and
the period of the at least one input window signal is shorter than or equivalent to the period of the periodic input signal.

16. The signal generator according to cla

Assignees

• Mediatek Inc

Inventors

• Chang Keng Meng
• Wang Yao Chi

Classifications

• H04L25/028

  Arrangements specific to the transmitter end · CPC title

• H03K19/0005

  Modifications of input or output impedance · CPC title

• H03L1/022

  by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature (H03L1/021 takes precedence) · CPC title

• H03L7/113

  using frequency discriminator · CPC title

• H04B1/1638

  Special circuits to enhance selectivity of receivers not otherwise provided for (resonant circuits H03H) · CPC title