Method for manufacturing a monolithic silicon wafer comprising multiple vertical junctions

Patent metadata

Field	Value
Publication number	US-9905716-B2
Application number	US-201314425968-A
Country	US
Kind code	B2
Filing date	Sep 3, 2013
Priority date	Sep 4, 2012
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

The present invention relates to a method for manufacturing a monolithic silicon wafer ( 10 ) comprising multiple vertical junctions ( 2 ) having an alternation of n-doped areas and p-doped areas, including at least the steps of: (i) providing a liquid bath ( 100 ) including silicon, at least one n-type doping agent and at least one p-type doping agent; (ii) proceeding to directionally solidify the silicon in a direction (I), varying the convection-diffusion parameters thereof in order to alternate the growth of n-doped silicon layers ( 101 ) and p-doped silicon layers ( 102 ); and (iii) cutting a slice ( 104 ), parallel to the direction (I), of the multi-layer structure obtained at the end of the step (ii), such as to obtain said expected wafer ( 10 ).

First claim

The invention claimed is:

1. A method for fabricating a monolithic silicon wafer with vertical multijunctions exhibiting an alternation of n-doped zones and of p-doped zones, comprising at least the steps consisting in:
(i) providing a liquid bath containing silicon, at least one n-type doping agent and at least one p-type doping agent;
(ii) proceeding to directionally solidifying the silicon in a direction, by varying the convection-diffusion parameters to alternate the growth of n-doped silicon layers and of p-doped silicon layers; and
(iii) cutting a slice, parallel to the direction, of the multilayer structure obtained on completion of the step (ii), so as to obtain said expected wafer,
wherein the step (ii) comprises, between the growth of an n-doped silicon layer and of a p-doped silicon layer, the growth of an intermediate layer, said intermediate layer exhibiting a resistivity greater than or equal to 80 Ω·m and a width in the cutting plane ranging from 50 μm to 5 mm.

2. The method as claimed in claim 1 , in which the step (ii) of solidifying the silicon is carried out by a pulling method.

3. The method as claimed in claim 1 , in which said p-type doping agent is chosen from boron (B), aluminum (Al), gallium (Ga), indium (In), zinc (Zn) and their mixtures.

4. The method as claimed in claim 1 , in which said p-type doping agent is boron.

5. The method as claimed in claim 1 , in which said n-type doping agent is chosen from phosphorous (P), arsenic (As), antimony (Sb), tin (Sn) and their mixtures.

6. The method as claimed in claim 1 , in which said n-type doping agent is antimony.

7. The method as claimed in claim 1 , in which said p-type doping agent is boron and said n-type doping agent is antimony.

8. The method as claimed in claim 1 , in which the variation of the convection-diffusion parameter in step (ii) is carried out via the variation of the rate of solidification of the silicon.

9. The method as claimed in claim 8 , in which the step (ii) is carried out by varying the rate of solidification of the silicon between at least a value V 1 conducive to the growth of the n-doped silicon, and a value V 2 conducive to the growth of the p-doped silicon.

10. The method as claimed in claim 8 , in which the solidification of the silicon in step (ii) is performed by a pulling method, the rate of solidification of the silicon being adjusted via the control of the pulling speed.

11. The method as claimed in claim 10 , in which the step (ii) is carried out by varying the rate of solidification of the silicon according to the repetition of the cycle V 1 -V 3 -V 2 -V 3 -, with V 1 being the rate conducive to the growth of the n-doped silicon, V 2 being the rate conducive to the growth of the p-doped silicon and V 3 being the rate conducive to the growth of said intermediate layer of intermediate value between V 1 and V 2 .

12. The method as claimed in claim 1 , in which the variation of the convection-diffusion parameter in step (ii) is carried out via the variation of the level of agitation of the liquid bath.

13. The method as claimed in claim 12 , in which the step (ii) is carried out by varying the level of agitation of the liquid bath between at least a value B 1 conducive to the growth of the n-doped silicon and a value B 2 conducive to the growth of the p-doped silicon.

14. The method as claimed in claim 12 , in which the level of agitation of the liquid bath is adjusted using an agitation system.

15. The method as claimed in claim 14 , in which the level of agitation of the liquid bath is adjusted by forced rotation of the crystal and/or of the crucible in a Czochralski-type pulling method, using an alternating magnetic field, rotating or sliding, a mechanical blade, a propeller or a disk.

16. The method as claimed in claim 1 , in which silicon, in solid or liquid form, is added into the liquid bath during the step (ii) in adequate quantities to compensate the enrichment of the liquid bath with n and p dopants as the silicon solidifies.

17. The method as claimed in claim 1 , in which the respective times in step (ii) for solidification of the n-doped silicon and of the p-doped silicon are adjusted in such a way that said n-doped and p-doped layers formed on completion of the step (ii) exhibit, independently of one another, a thickness of at least 2 mm.

18. The method as claimed in claim 1 , in which the respective times in step (ii) for solidification of the n-doped silicon and of the p-doped silicon are adjusted in such a way that said n-doped and p-doped layers formed on completion of the step (ii) exhibit, independently of one another, a thickness ranging from 2 mm to 10 cm.

19. The method as claimed in claim 1 , in which the respective times in step (ii) for solidification of the n-doped silicon and of the p-doped silicon are adjusted in such a way that said n-doped and p-doped layers formed on completion of the step (ii) exhibit, independently of one another, a thickness ranging from 5 mm to 5 cm.

20. A monolithic silicon wafer with vertical multi-junctions, exhibiting, in at least one vertical cutting plane, an alternation of n-doped zones and of p-doped zones, each of the zones extending over the entire thickness of the wafer and having a width in the cutting plane of at least 2 mm,
wherein said n-doped zones and said p-doped zones are separated from one another by at least one intermediate zone, said intermediate zone exhibiting a resistivity greater than or equal to 80 Ω·m and a width in the cutting plane ranging from 50 μm to 5 mm.

21. The wafer as claimed in claim 20 , said wafer being formed according to a method for fabricating a monolithic silicon wafer with vertical multijunctions exhibiting an alternation of n-doped zones and of p-doped zones, comprising at least the steps consisting in:
(i) providing a liquid bath containing silicon, at least one n-type doping agent and at least one p-type doping agent;
(ii) proceeding to directionally solidifying the silicon in a direction, by varying the convection-diffusion parameters to alternate the growth of n-doped silicon layers and of p-doped silicon layers; and
(iii) cutting a slice, parallel to the direction, of the multilayer structure obtained on completion of the step (ii), so as to obtain said expected wafer.

22. The wafer as claimed in claim 20 , in which said n-doped zones exhibit, independently of one another, an electron-type charge carrier density ranging from 10 14 to 10 17 cm −3 .

23. The wafer as claimed in claim 20 , in which said n-doped zones exhibit, independently of one another, a width in the cutting plane ranging from 2 mm to 10 cm.

24. The wafer as claimed in claim 20 , in which said n-doped zones exhibit, independently of one another, a width in the cutting plane ranging from 5 mm to 5 cm.

25. The wafer as claimed in claim 20 , in which said p-doped zones exhibit, independently of one another, a hole-type charge carrier density ranging from 10 14 to 10 17 cm −3 .

26. The wafer as claimed in claim 20 , said p-doped zones exhibiting, independently of one another, a width in the cutting plane ranging from 2 mm to 10 cm.

27. The wafer as claimed in claim 20 , in which said p-doped zones exhibit, independently of one another, a width in the cutting plane ranging from 5 mm to 5 cm.

28. The wafer as claimed in claim 20 , in which each of said intermediate zones exhibits

Assignees

• Commissariat Energie Atomique
• Commissariat Energie Atomique

Inventors

• Garandet Jean Paul
• Chaintreuil Nicolas
• Fasiello Annalaura
• Pilat Eric
• Veschetti Yannick

Classifications

• H01L31/1804

  Electricity · mapped topic

• C30B15/04

  adding doping materials, e.g. for n-p-junction · CPC title

• Y02E10/547

  Monocrystalline silicon PV cells · CPC title

• H01L31/0687

  Electricity · mapped topic

• Y02P70/521

  Cross-Sectional Technologies · mapped topic