Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9905569-B1
Application number	US-201715472720-A
Country	US
Kind code	B1
Filing date	Mar 29, 2017
Priority date	Aug 24, 2016
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A method of forming a nonvolatile memory device includes forming first, second, and third gate structures, with the second and third gate structures including first and second spacer structures formed on a sidewall of the second gate structure and sidewalls of the third gate structure. Impurity regions are formed through ion implantation and the first spacer structure shields the second and third gate structures during ion implantation. The second spacer structure defines resulting impurity regions.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a gate structure layer on a substrate;
partially etching the gate structure layer to form a plurality of first gate structures on a region of the substrate through a first patterning process, wherein each of the plurality of first gate structures has a first width;
forming a capping insulation layer covering an upper portion of the plurality of first gate structures and the gate structure layer;
partially etching the capping insulation layer and the gate structure layer to form a plurality of second gate structures having sidewalls and a plurality of first capping insulation patterns through a second patterning process, wherein each of the plurality of second gate structures has a second width greater than the first width, and sidewalls of neighboring ones of the plurality of second gate structures opposing each other;
forming a first spacer structure on sidewalls of each of the plurality of second gate structures and each of the plurality of first capping insulations, the first spacer structure including a first spacer and a second spacer; and
forming an impurity region at an upper portion of the substrate between the plurality of first gate structures.

2. The method of claim 1 , wherein forming the first spacer structure includes:
forming a first spacer layer on a sidewall of each of the plurality of second gate structures and a sidewall and an upper surface of each of the plurality of first capping insulation patterns and an upper surface of the substrate;
forming a second spacer layer on the first spacer layer; and
anisotropically etching the first and second spacer layers to form the first and second spacers, respectively.

3. The method of claim 2 , further comprising, after forming the first spacer layer, implanting impurities into the substrate to form an impurity extension region.

4. The method of claim 2 , wherein the second spacer layer is formed of an insulation material different from an insulation material of the first spacer layer.

5. The method of claim 1 , wherein forming the gate structure layer includes:
forming a preliminary gate insulation layer, a first conductive layer, a dielectric layer and a second conductive layer;
partially etching the second conductive layer and the dielectric layer on a region for forming the second gate structure to form a recess exposing the first conductive layer;
forming a third conductive layer on a surface of the second conductive layer and on an inner wall of the recess; and
forming a mask layer on the third conductive layer.

6. The method of claim 5 , wherein the third conductive layer is formed of a metal or a metal nitride.

7. The method of claim 5 , wherein each of the first and second gate structures includes a gate insulation layer, a first conductive pattern, a dielectric pattern, a second conductive pattern and a third conductive pattern sequentially stacked, and the first, second and third conductive patterns in each of the plurality of second gate structures are electrically connected to each other.

8. The method of claim 1 , wherein the second patterning process includes:
forming a first photoresist pattern on the capping insulation layer; and
etching the capping insulation layer and the gate structure layer using the first photoresist pattern as an etching mask to form the plurality of second gate structures and the plurality of first capping insulation patterns, a first opening being between neighboring ones of the plurality of second gate structures.

9. The method of claim 1 , wherein the second patterning process includes:
forming a first photoresist pattern on the capping insulation layer; and
etching the capping insulation layer and an upper portion of the gate structure layer using the first photoresist as an etching mask to form a plurality of preliminary first capping insulation patterns and a preliminary first opening between neighboring ones of the plurality of preliminary first capping insulation patterns;
isotropically etching a surface of the first photoresist pattern to form a second photoresist pattern; and
etching the plurality of preliminary first capping insulation patterns and the gate structure layer using the second photoresist as an etching mask to form the plurality of second gate structures and the plurality of first capping insulation patterns, a first opening being between neighboring ones of the plurality of second gate structures, and a sidewall of each of the plurality of first capping insulation patterns having an inflection point.

10. The method of claim 1 , wherein, when the second patterning process is performed, a third gate structure and a second capping insulation pattern are also formed on the substrate, and wherein the third gate structure has a third width greater than the second width.

11. The method of claim 10 , wherein, when the first spacer structure is formed, a second spacer structure is also formed on sidewalls of the third gate structure and the second capping insulation pattern, and wherein the second spacer structure has a third spacer and a fourth spacer.

12. The method of claim 11 , wherein the capping insulation layer is formed to cover upper portions of the first, second and third gate structures and to not fill a space between the plurality of first gate structures, so that an air gap is formed between neighboring ones of the plurality of first gate structures.

13. A method of forming a semiconductor device, the method comprising:
forming a gate structure layer on a first region and a second region of a substrate;
partially etching the gate structure layer to form a plurality of first gate structures on the first region through a first patterning process, each of the plurality of first gate structures having a first width;
forming a capping insulation layer covering the plurality of first gate structures and the gate structure layer;
partially etching the capping insulation layer and the gate structure layer to form a plurality of second gate structures, a first capping insulation pattern covering upper portions of the first and second gate structures, and a third gate structure and a second capping insulation pattern on the second region through a second patterning process, wherein each of the plurality of second gate structures has a second width greater than the first width, and sidewalls of neighboring ones of the plurality of second gate structures oppose each other, and wherein the third gate structure has a third width greater than the second width;
forming a first spacer layer on surfaces of the second and third gate structures, the first and second capping insulation pattern, and the substrate;
forming a second space layer on the first spacer layer; and
anisotropically etching the first and second spacer layers to form a first spacer structure on sidewalls of each of the plurality of second gate structures and the first capping insulation pattern and a second spacer structure on sidewalls of the third gate structure and second capping insulation pattern, the first spacer structure including a first spacer and a second spacer, and the second spacer including a third spacer and a fourth spacer.

14. The method of claim 13 , wherein each of the first and second gate structures includes a gate insulation layer, a first conductive pattern, a dielectric pattern, a second conductive pattern and a third conductive pattern sequentially stacked, and the first, second and third conductive patterns in each of the plurality of second gate structures are electrically connected to each other.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dong Won
• Park Bong Tae
• Seong Ho Jun
• Sim Jae Hwang
• Jun Jung Hoon

Classifications

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/264

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title