Mask read-only memory device and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-9905566-B2
Application number	US-201614989494-A
Country	US
Kind code	B2
Filing date	Jan 6, 2016
Priority date	Jan 7, 2015
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

The disclosed subject matter provides a mask read-only memory (M-ROM) device and fabrication method thereof. In an M-ROM device, a first layer having a first type doping is formed in a substrate. A plurality of buried lines is formed in the first layer of the substrate. The plurality of buried lines are arranged in parallel in a first direction and isolated from each other. An epitaxial growth process is used to form a second layer on the first layer of the substrate. A plurality of diodes is formed in the second layer. The plurality of diodes is arranged in an array. Each diode includes a first electrode having a second type doping and connecting with one of the plurality of buried lines, and a second electrode having a first type doping and located on the first electrode.

First claim

What is claimed is:

1. A method for fabricating a mask read-only memory device comprising:
providing a first substrate including a first region and a second region;
forming a first layer having a first type doping in the first region of the first substrate;
forming a second substrate on the first region and the second region of the first substrate;
forming a first isolation structure in the second substrate and partially in the first substrate between the first region and the second region;
forming a plurality of diodes in the second substrate and on the first layer of the first substrate, wherein the plurality of diodes are arranged in an array,
wherein each diode comprises:
a first electrode having a second type doping and connecting with a buried line, and
a second electrode having a first type doping and located on the first electrode; and

forming a metal-oxide-semiconductor (MOS) transistor in the second substrate above the second region of the first substrate.

2. The method of claim 1 , wherein forming a second substrate on the first region and the second region of the first substrate comprises:
using an epitaxial process temperature between 950° C. to 1150° C.; and
using an epitaxial process gas of dichlorosilane.

3. The method of claim 1 , wherein forming a second substrate on the first region and the second region of the first substrate comprises:
using an epitaxial process temperature between 500° C. to 900° C.; and
using an epitaxial process gas selected from a group of SiH 4 , SiHCl 3 , and their combination.

4. The method of claim 1 , wherein the first type doping is N-type ions doping, and the second type doping is P-type ions doping.

5. The method of claim 4 , wherein:
the first electrode is heavily doped with dopant ions selected from As, P, Sb, and their combination; and
the second electrode is lightly doped with dopant ions selected from B and BF 2 .

6. The method of claim 1 , further comprising:
forming a plurality of second isolation structures in the second substrate to isolate the plurality of diodes from each other in a first direction.

7. The method of claim 6 , wherein:
each second isolation structure comprises a shallow trench having a depth no less than a thickness of the plurality of diodes.

8. The method of claim 1 , further comprising:
forming a plurality of lead regions in the first region of the second substrate, wherein:
the lead regions have a first type doping, and
the lead regions and the second electrode are formed in a same process.

9. The method of claim 8 , wherein the first isolation structure isolates the plurality of lead regions and the first layer from a well region of the MOS transistor.

10. The method of claim 1 , wherein forming the MOS transistor comprises:
forming a well region of the MOS transistor in the second substrate, wherein:
the well region has a second type doping, and
the well region and the first electrode are formed in a same process;

forming a gate electrode of the MOS transistor on the well region; and
forming a source electrode and a drain electrode of the MOS transistor in the well region, wherein:
the source electrode and the drain electrode have a first type doping, and
the source electrode, the drain electrode, and the second electrode are formed in a same process.

11. The method of claim 10 , further comprising:
forming a third isolation structure in the second region of the second substrate to isolate the well region and the lead region;
wherein the plurality of second isolation structures and the third isolation structure are formed in a same process.

12. The method of claim 10 , further comprising:
performing an annealing process to activate doped ions in the first electrode and the well region, wherein:
the annealing process has an annealing temperature range from 950° C. to 1150° C., and
the annealing process has an annealing time range from 10 s to 120 min.

13. The method of claim 1 , wherein the first substrate further includes a third layer having a second type doping, the first layer is formed on the third layer.

14. The method of claim 13 , wherein the first isolation structure extends into the third layer of the first substrate.

Assignees

• Semiconductor Mfg Int Shanghai Corp

Inventors

• Zhang Chao
• Chan Yipeng

Classifications

• H01L27/11253 Primary

  Electricity · mapped topic

• H01L27/112

  Electricity · mapped topic

• H10B20/38 Primary

  Doping programmed, e.g. mask ROM · CPC title

• H10B20/00

  Read-only memory [ROM] devices · CPC title