Semiconductor package and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-9905550-B2
Application number	US-201514736247-A
Country	US
Kind code	B2
Filing date	Jun 10, 2015
Priority date	Jul 11, 2014
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

Embodiments of the inventive concepts provide a semiconductor package and a method of fabricating the same. The method includes forming a groove to separate first semiconductor chips from each other. Forming the groove include performing a first sawing process on a bottom surface of a semiconductor substrate to cut the semiconductor substrate and a portion of a mold layer in a direction inclined with respect to the bottom surface, and performing a second sawing process to cut the mold layer in a direction substantially perpendicular to the bottom surface of the semiconductor substrate. A minimum width of the groove formed in the semiconductor substrate by the first sawing process may be greater than a width of the groove formed in the mold layer by the second sawing process.

First claim

What is claimed is:

1. A method of fabricating a semiconductor package, the method comprising:
providing a semiconductor substrate having a top surface on which chip stacks are mounted, each of the chip stacks comprising a plurality of stacked semiconductor chips;
forming a mold layer covering the chip stacks on the top surface of the semiconductor substrate; and
forming a groove penetrating the semiconductor substrate and the mold layer by performing a sawing process on a bottom surface of the semiconductor substrate,
wherein the groove comprises:
first sidewalls adjacent to the top surface of the semiconductor substrate and extending in a direction inclined with respect to the bottom surface of the semiconductor substrate;
second sidewalls connected to the first sidewalls and extending in a direction substantially perpendicular to the bottom surface of the semiconductor substrate; and
edges formed at a location the first sidewalls meet the second sidewalls,
wherein the edges are formed in the mold layer.

2. The method of claim 1 , wherein a maximum width of the groove formed in the semiconductor substrate is greater than a maximum width of the groove formed in the mold layer.

3. The method of claim 1 , wherein forming the groove comprises:
sawing the semiconductor substrate from the bottom surface of the semiconductor substrate toward the mold layer to form a first groove having the first sidewalls, the mold layer being exposed along the first sidewalls of the first groove; and
sawing the mold layer exposed by the first groove to form a second groove having the second sidewalls.

4. The method of claim 1 , wherein the first sidewall makes an obtuse angle with the bottom surface of the semiconductor substrate.

5. The method of claim 1 , wherein the semiconductor substrate includes base semiconductor chips having through-vias penetrating the base semiconductor chips, and
wherein each of the chip stacks are electrically connected to a corresponding base semiconductor chip.

6. The method of claim 5 , wherein the semiconductor substrate is divided into the base semiconductor chips by the groove and the mold layer is divided into unit mold layers by the groove, and
wherein a distance between a pair of adjacent base semiconductor chips is greater than a distance between a pair of adjacent unit mold layers.

7. The method of claim 1 , wherein active surfaces of the semiconductor chips of the chip stacks face the semiconductor substrate.

8. The method of claim 1 , wherein the groove penetrates the mold layer disposed between a pair of adjacent chip stacks.

9. The method of claim 1 , wherein the semiconductor substrate comprises: a passivation layer covering the bottom surface; and external terminals formed on the bottom surface, and
wherein the passivation layer is exposed.

10. A method of fabricating a semiconductor package, the method comprising:
preparing a semiconductor substrate including first semiconductor chips;
mounting second semiconductor chips on a top surface of the semiconductor substrate;
forming a mold layer covering the second semiconductor chips on the top surface of the semiconductor substrate; and
forming a groove penetrating the semiconductor substrate and the mold layer to separate the first semiconductor chips from each other,
wherein forming the groove comprises:
performing a first sawing process on a bottom surface of the semiconductor substrate to cut the semiconductor substrate and a portion of the mold layer in a direction inclined with respect to the bottom surface of the semiconductor substrate; and
performing a second sawing process to cut the mold layer in a direction substantially perpendicular to the bottom surface of the semiconductor substrate,
wherein a minimum width of the groove formed in the semiconductor substrate by the first sawing process is greater than a width of the groove formed in the mold layer by the second sawing process.

11. The method of claim 10 , wherein the second sawing process is performed to be spaced apart from the semiconductor substrate.

12. The method of claim 10 , wherein the groove formed by the first sawing process has inclined sidewalls, and
wherein the semiconductor substrate and the mold layer are exposed along the inclined sidewalls.

13. The method of claim 10 , wherein the first semiconductor chip comprises:
a first integrated circuit layer;
a passivation layer covering the first integrated circuit layer;
a first through-via penetrating the first semiconductor chip and connected to the first integrated circuit layer; and
an external terminal electrically connected to the first integrated circuit layer,
wherein the passivation layer is exposed.

14. The method of claim 10 , further comprising:
mounting third semiconductor chips on the second semiconductor chips,
wherein each of the second semiconductor chips has a through-via penetrating the corresponding second semiconductor chip.

15. The method of claim 10 , wherein the semiconductor substrate is divided into the first semiconductor chips by the first sawing process,
wherein the mold layer is divided into unit mold layers by the second sawing process, and
a minimum distance between a pair of adjacent first semiconductor chips is greater than a minimum distance between a pair of adjacent unit mold layers respectively disposed on the first semiconductor chips adjacent to each other.

16. A method of fabricating a semiconductor package, the method comprising:
providing a semiconductor substrate having a top surface on which chip stacks are mounted, each of the chip stacks comprising a plurality of stacked semiconductor chips;
forming a mold layer covering the chip stacks on the top surface of the semiconductor substrate; and
forming a first groove penetrating the semiconductor substrate, the first groove having first sidewalls inclined with respect to a bottom surface of the semiconductor substrate; and
forming a second groove penetrating the mold layer extending in a direction substantially perpendicular to the bottom surface of the semiconductor substrate to form package units separated from each other,
wherein the second groove comprise second sidewalls connected to the first sidewalls, the second groove exposed through the first groove.

17. The method of claim 16 , wherein edges are formed at a location where the first sidewalls meet the second sidewalls, and wherein the edges are formed in the mold layer.

18. The method of claim 16 , wherein edges are formed at a location where the first sidewalls meet the second sidewalls, and wherein the edges are formed on sidewalls of the semiconductor chips.

19. The method of claim 16 , wherein forming the first groove comprises performing a sawing process using a blade having a substantially V-shaped cross-section on the bottom surface of the semiconductor substrate toward the mold layer to form the first groove, wherein forming the second groove comprises performing another sawing process on the mold layer exposed through the first groove using a second blade having a substantially rectangular cross-section.

20. The method of claim 16 , wherein a width of the second groove formed in the mold layer is smaller than a width of the first groove at the bottom surface of the semiconductor substrate, and wherein the width of the second groove formed in the mold layer is substantially equal to a width of the first groove at the top surface of the semiconductor substrate.

Assignees

• Han Sang Uk
• Park Seungwon
• Kang Un Byoung
• Cho Taeje
• Samsung Electronics Co Ltd

Inventors

• Han Sang Uk
• Park Seungwon
• Kang Un Byoung
• Cho Taeje

Classifications

• H10D62/117

  Shapes of semiconductor bodies · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title