Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9905516-B2
Application number	US-201514847461-A
Country	US
Kind code	B2
Filing date	Sep 8, 2015
Priority date	Sep 26, 2011
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A metal oxide layer is in contact with an interlayer insulating layer covering a transistor, and has a stacked-layer structure including a first metal oxide layer having an amorphous structure and a second metal oxide layer having a polycrystalline structure. In the first metal oxide layer, there are no crystal grain boundaries, and grid intervals are wide as compared to those in a metal oxide layer in a crystalline state; thus, the first metal oxide layer easily traps moisture between the lattices. In the second metal oxide layer having a polycrystalline structure, crystal parts other than crystal grain boundary portions have dense structures and extremely low moisture permeability. Thus, the structure in which the metal oxide layer including the first metal oxide layer and the second metal oxide layer is in contact with the interlayer insulating layer can effectively prevent moisture permeation into the transistor.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor layer;
a gate insulating layer adjacent to the semiconductor layer;
a gate electrode adjacent to the semiconductor layer with the gate insulating layer interposed therebetween;
a pair of electrodes electrically connected to the semiconductor layer;
a metal oxide layer covering the pair of electrodes; and
a pair of wirings electrically connected to the pair of electrodes, respectively, through openings opened in the metal oxide layer,
wherein the metal oxide layer has a stacked-layer structure at least comprising:
a first metal oxide layer having an amorphous structure; and
a second metal oxide layer having a polycrystalline structure.

2. The semiconductor device according to claim 1 , further comprising an insulating layer between the pair of electrodes and the metal oxide layer.

3. The semiconductor device according to claim 1 , further comprising an insulating layer over the metal oxide layer.

4. The semiconductor device according to claim 1 , further comprising an insulating layer over the metal oxide layer,
wherein the first metal oxide layer is placed over the pair of electrodes, and
wherein the second metal oxide layer is placed over the first metal oxide layer.

5. The semiconductor device according to claim 1 , further comprising an insulating layer over the pair of electrodes,
wherein the first metal oxide layer is placed over the insulating layer, and
wherein the second metal oxide layer is placed over the first metal oxide layer.

6. The semiconductor device according to claim 1 , wherein the semiconductor layer is a film including an oxide semiconductor material.

7. The semiconductor device according to claim 1 ,
wherein the pair of electrodes are in contact with a top surface of the semiconductor layer, and
wherein the gate electrode is placed over the semiconductor layer.

8. The semiconductor device according to claim 1 ,
wherein the semiconductor layer is placed over the gate electrode, and
wherein the pair of electrodes are in contact with a top surface of the semiconductor layer.

9. The semiconductor device according to claim 1 ,
wherein the semiconductor layer is placed over the gate electrode, and
wherein the semiconductor layer is in contact with top surfaces of the pair of electrodes.

10. A semiconductor device comprising:
a semiconductor region;
a gate insulating layer over the semiconductor region;
a gate electrode over the gate insulating layer;
a metal oxide layer over the gate electrode; and
a pair of wirings over the metal oxide layer, the pair of wirings being electrically connected to the semiconductor region through openings opened in the metal oxide layer,
wherein the metal oxide layer has a stacked layer structure at least comprising:
a first metal oxide layer having an amorphous structure; and
a second metal oxide layer having a polycrystalline structure.

11. The semiconductor device according to claim 10 , further comprising an insulating layer between the gate electrode and the metal oxide layer.

12. The semiconductor device according to claim 10 , further comprising an insulating layer over the metal oxide layer.

13. The semiconductor device according to claim 10 , wherein the semiconductor region includes an oxide semiconductor material.

14. A semiconductor device comprising:
an oxide semiconductor layer;
a gate insulating layer over the oxide semiconductor layer;
a gate electrode over the gate insulating layer;
an insulating layer including silicon oxynitride over the gate electrode;
a first metal oxide layer including aluminum oxide over the insulating layer;
a second metal oxide layer including aluminum oxide over the first metal oxide layer; and
a pair of wirings over the second metal oxide layer, the pair of wirings being electrically connected to the oxide semiconductor layer through openings opened in the first metal oxide layer and the second metal oxide layer.

15. The semiconductor device according to claim 14 , wherein the first metal oxide layer has an amorphous structure, and the second metal oxide layer has a polycrystalline structure.

16. The semiconductor device according to claim 14 , wherein the second metal oxide layer is in contact with the first metal oxide layer.

Assignees

• Semiconductor Energy Lab

Inventors

• Watanabe Masahiro
• Mashiyama Mitsuo
• Handa Takuya
• Okazaki Kenichi

Classifications

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H01L29/78606

  Electricity · mapped topic

• H01L2924/00

  Electricity · mapped topic

• H01L23/564 Primary

  Electricity · mapped topic

• H01L29/7869

  Electricity · mapped topic