Semiconductor memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9905510-B2
Application number	US-201715433451-A
Country	US
Kind code	B2
Filing date	Feb 15, 2017
Priority date	Feb 17, 2016
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

According to one embodiment, a semiconductor memory device includes, a first interconnect layer provided on a first insulating layer and including a first conductive layer, a second interconnect layer provided on a second insulating layer above the first interconnect layer and including a second conductive layer having a composition different from that of the first conductive layer, and a pillar extending through the first and second insulating layers and the first and second interconnect layers and including a semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer, which are stacked on a side surface of the semiconductor layer.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a first interconnect layer provided on a first insulating layer above a semiconductor substrate and including a first conductive layer;
a second interconnect layer provided on a second insulating layer above the first interconnect layer and including a second conductive layer having a composition different from that of the first conductive layer; and
a pillar extending through the first and second insulating layers and the first and second interconnect layers and including a semiconductor layer, and a third insulating layer, a charge storage layer, and a fourth insulating layer, which are stacked on a side surface of the semiconductor layer.

2. The device according to claim 1 , wherein a resistivity of the first conductive layer is different from a resistivity of the second conductive layer.

3. The device according to claim 1 , wherein
the first and second conductive layers are made of the same element, and
a concentration of an impurity contained in the first conductive layer is different from a concentration of an impurity contained in the second conductive layer.

4. The device according to claim 1 , wherein each of the first and second conductive layers contains tungsten.

5. The device according to claim 3 , wherein the impurity contained in each of the first and second conductive layers is fluorine.

6. The device according to claim 3 , wherein the concentration of the impurity contained in the first conductive layer is higher than the concentration of the impurity contained in the second conductive layer.

7. The device according to claim 1 , wherein
the first interconnect layer further including a first barrier layer covering part of the first conductive layer,
the second interconnect layer further including a second barrier layer covering part of the second conductive layer, and
each of the first and second barrier layers contains titanium nitride.

8. The device according to claim 7 , wherein
the first barrier layer covers an upper surface, a bottom surface, and one side surface of the first conductive layer, and contacts a side surface of the pillar, and
the second barrier layer covers an upper surface, a bottom surface, and one side surface of the second conductive layer, and contacts a side surface of the pillar.

9. The device according to claim 1 , further comprising:
a first plug having a bottom surface contacting the first interconnect layer; and
a second plug having a bottom surface contacting the second interconnect layer,
wherein when a length of the first interconnect layer from the first plug to the pillar is set as a first interconnect length,
a length of the second interconnect layer from the second plug to the pillar is set as a second interconnect length,
a sectional area of the first interconnect layer in a direction perpendicular to a direction in which the first interconnect layer extends is set as a first area in a region where the pillar extends through the first interconnect layer,
a sectional area of the second interconnect layer in a direction perpendicular to a direction in which the second interconnect layer extends is set as a second area in a region where the pillar extends through the second interconnect layer,
a ratio between the first interconnect length and the first area is set as a first ratio, and
a ratio between the second interconnect length and the second area is set as a second ratio,
a resistivity of one of the first and second interconnect layers, which has a higher one of the first ratio and the second ratio, is lower than a resistivity of other of the first and second interconnect layers, which has a lower ratio.

10. The device according to claim 1 , wherein
the pillar includes a first pillar and a second pillar,
the first pillar extends through the first interconnect layer and includes the semiconductor layer, and the third insulating layer, the charge storage layer, and the fourth insulating layer, which are stacked on the side surface of the semiconductor layer, and
the second pillar extends through the second interconnect layer, has a bottom surface contacting an upper surface of the first pillar, and includes the semiconductor layer, and the third insulating layer, the charge storage layer, and the fourth insulating layer, which are stacked on the side surface of the semiconductor layer.

Assignees

• Toshiba Memory Corp

Inventors

• Komori Yosuke

Classifications

• H10W20/425 Primary

  Barrier, adhesion or liner layers · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title