3D non-volatile memory array with sub-block erase architecture

Patent metadata

Field	Value
Publication number	US-9721668-B2
Application number	US-201514820209-A
Country	US
Kind code	B2
Filing date	Aug 6, 2015
Priority date	Aug 6, 2015
Publication date	Aug 1, 2017
Grant date	Aug 1, 2017

Abstract

A memory device has a divided reference line structure which supports sub-block erase in NAND memory including a plurality of blocks. Each block in the plurality of blocks is coupled to a set of Y reference lines, where Y is two or more. Each block in the plurality of blocks includes a single reference select line (RSL), which is operable to connect each sub-block in the block to a corresponding reference line in the set of Y reference lines. A control circuit can be included on the device which is configured for an erase operation to erase a selected sub-block in a selected block.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of blocks of memory cells, bit lines, word lines and sub-block reference lines;
each block in the plurality being operably coupled to a set of X bit lines BL(x), a set of Z word lines WL(z), and a set of Y sub-block reference lines RL(y), where Y is two or more, and each block including:
an array of NAND strings including a plurality of rows and a plurality of columns of NAND strings, each NAND string in the array including memory cells coupled to each word line WL(z) in the set of Z word lines, the NAND strings in the array having respective first select switches and second select switches;
a string select line set including N string select lines coupled to gates of the first select switches of NAND strings in corresponding columns of the NAND strings in the array, each string select line SSL(n) in the string select line set configured to control the first switches in one column of the NAND strings in the array for selective connection to corresponding bit lines BL(x) in the set of X bit lines;
a reference select line RSL coupled to gates of the second select switches of all the NAND strings in the array, the reference select line RSL configured to control the second switches in the array for connection of NAND strings in Y sub-blocks of the array to corresponding reference lines RL(y) in the set of Y sub-block reference lines, the NAND strings in a same row connected to two or more reference lines RL(y) in the set of Y sub-block reference lines; and
a controller and bias circuitry coupled to the plurality of blocks, responsive to a command to erase a selected sub-block in a selected block, to apply an erase bias arrangement including a first bias on the reference select line of the selected block, a second bias on a selected one of the Y sub-block reference lines to induce erase current in the selected sub-block, and a third bias on at least one unselected reference line of the Y sub-block reference lines to inhibit erase current in the NAND strings of one or more unselected sub-block in the selected block.

2. The memory device of claim 1 , wherein the NAND strings are disposed vertically with a plurality of word line levels, one word line for each NAND string in each word line level, the string select lines in an upper level above the word line levels, and the reference select line in a lower level below the word line levels.

3. The memory device of claim 1 , wherein the NAND strings are disposed vertically in a U-shape, with a plurality of word line levels, two word lines for each NAND string in each word line level, the string select lines in an upper level above the word line levels, and the reference select line in said upper level.

4. The memory device of claim 1 , wherein the second bias on a selected one of the Y sub-block reference lines is set to cause gate induced drain leakage GIDL current as said erase current in the NAND strings of the selected sub-block.

5. The memory device of claim 1 , the erase bias arrangement including a common bias to the word lines WL(z) in the set of Z word lines.

6. The memory device of claim 1 , the erase bias arrangement including floating the bit lines BL(x) in the set of X bit lines, and floating the string select lines SSL(n) in the set of N string select lines.

7. The memory device of claim 1 , the erase bias arrangement configured to induce hole tunneling to erase the memory cells in the selected sub-block.

8. A memory device, comprising:
a plurality of blocks of memory cells, each block in the plurality being operably coupled to a set of X bit lines BL(x), a set of Z word lines WL(z), and a set of Y sub-block reference lines RL(y), where Y is two or more, and each block including:
a plurality of stacks of conductive strips, the plurality of stacks including even stacks and odd stacks;
a plurality of active pillars arranged between corresponding even and odd stacks of conductive strips in the plurality of stacks, active pillars in the plurality comprising even and odd vertical channel films having outside surfaces and inside surfaces, defining a multi-layer array of interface regions at cross-points between outside surfaces of the even and odd vertical channel films and conductive strips in the corresponding even and odd stacks of conductive strips, the even and odd vertical channel films are connected to form a current path from an upper end to a lower end of the even vertical channel film, and from a lower end to an upper end of the odd vertical channel film;
a 3D array of NAND strings including a plurality of rows and a plurality of columns of NAND strings and including even memory cells in the interface regions accessible via the active pillars and conductive strips in the even stacks of conductive strips and odd memory cells in the interface regions accessible via the active pillars and conductive strips in the odd stacks of conductive strips, wherein the even and odd memory cells on a given active pillar are connected in series as a single NAND string;
conductive strips in an upper level in the even stacks being configured as a string select line set including N string select lines, each string select line SSL(n) in the string select line set configured to control string select switches in one column of the NAND strings in the array for selective connection to corresponding bit lines BL(x) in a set of X bit lines;
conductive strips in an upper level in the odd stacks being configured as a common reference select line RSL configured to control reference select switches in all the NAND strings in the array, for connection of NAND strings in Y sub-blocks of the array to corresponding reference lines RL(y) in the set of Y sub-block reference lines, the NAND strings in a same row connected to two or more reference lines RL(y) in the set of Y sub-block reference lines;
conductive strips in intermediate levels in the even and odd stacks being configured as word lines for the NAND string on a given active pillar, and

a controller and bias circuitry coupled to the plurality of blocks, responsive to a command to erase a selected sub-block in a selected block, to apply an erase bias arrangement including a first bias on the reference select line of the selected block, a second bias on a selected one of the Y sub-block reference lines to induce erase current in the selected sub-block, and a third bias on at least one unselected reference line of the Y sub-block reference lines to inhibit erase current in the NAND strings of one or more unselected sub-block in the selected block.

9. The memory device of claim 8 , including one or more patterned conductor layers over the plurality of stacks, including said bit lines and said reference lines, and interlayer connectors connecting the bit lines to corresponding even vertical channel films and connecting said reference lines to corresponding odd vertical channel films.

10. The memory device of claim 8 , wherein in a given block, conductive strips in a given layer of an odd stack are configured in a comb-like structure with strips extending from an odd pad, and conductive strips in the given layer of an even stack are configured in a comb-like structure with strips extending from an even pad, the conductive strips extending from the odd and even pads in the given block being interdigitated.

11. The memory device of claim 8 , wherein the memory cells comprise charge storage structures.

12. The memory device of claim 8 , wherein the second bias on a selected one of the Y sub-block reference lines is set to cause gate induced drain leakage GIDL current as said erase current in the NAND strings of the selected sub-block.

Assignees

• Macronix Int Co Ltd

Inventors

• Yeh Teng-Hao
• Chang Kuo-Pin

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• H01L27/24

  Electricity · mapped topic

• G11C16/14 Primary

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• H10B43/00

  EEPROM devices comprising charge-trapping gate insulators · CPC title