Error correction hardware with fault detection

Patent metadata

Field	Value
Publication number	US-9904595-B1
Application number	US-201615244739-A
Country	US
Kind code	B1
Filing date	Aug 23, 2016
Priority date	Aug 23, 2016
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

First claim

The invention claimed is:

1. Error correction code (ECC) hardware for a single port memory circuit, comprising:
write path circuitry including write generation (Gen) ECC logic for generating first ECC bits from write data and for writing said first ECC bits and said write data to said memory circuit;
read path circuitry including a check ECC block for coupling read data from said memory circuit comprising read Gen ECC logic coupled to an XOR circuit that has an input for coupling to an ECC output of said memory circuit, wherein an output of said XOR circuit provides a syndrome signal to a syndrome decode block coupled to a single bit error correction (SEC) block and for generating a multi-bit error detection (MED) interrupt signal;
a first multiplexer (MUX) having a first input for receiving said write data in series with an input to said write ECC generation logic or a second MUX having a first input for receiving said read data from said memory circuit in series with an input of said read Gen ECC logic;
a cross-coupling connector for coupling said read data from said memory circuit to a second input of said first MUX or a cross-coupling connector for coupling said write data to a second input of said second MUX, and
an ECC bit comparator for comparing an output of said write Gen ECC logic to an output of said read Gen ECC logic.

2. The ECC hardware of claim 1 , wherein an output of said comparator is coupled as an enable input to said syndrome decode block and as an enable input to said SEC block.

3. The ECC hardware of claim 1 , wherein said ECC hardware and said single port memory circuit are formed on a common substrate having at least a semiconductor surface.

4. The ECC hardware of claim 1 , wherein said ECC hardware includes said first MUX and said second MUX.

5. Error correction code (ECC) hardware for a single port memory circuit, comprising:
write path circuitry including write generation (Gen) ECC logic for generating first ECC bits from write data and for writing said first ECC bits and said write data to said memory circuit;
read path circuitry including a check ECC block for coupling read data from said memory circuit comprising read Gen ECC logic coupled to an XOR circuit that has an input for coupling to an ECC output of said memory circuit, wherein an output of said XOR circuit provides a syndrome signal to a syndrome decode block coupled to a single bit error correction (SEC) block and for generating a multi-bit error detection (MED) interrupt signal;
a first multiplexer (MUX) having a first input for receiving said write data in series with an input to said write ECC generation logic and a second MUX having a first input for receiving said read data from said memory circuit in series with an input of said read Gen ECC logic;
a cross-coupling connector for coupling said read data from said memory circuit to a second input of said first MUX and a cross-coupling connector for coupling said write data to a second input of said second MUX;
an ECC bit comparator for comparing an output of said write Gen ECC logic received to an output of said read Gen ECC logic.

6. The ECC hardware of claim 5 , wherein an output of said comparator is coupled as an enable input to said syndrome decode block and as an enable input to said SEC block.

7. The ECC hardware of claim 5 , wherein said ECC hardware and said single port memory circuit are formed on a common substrate having at least a semiconductor surface.

8. An Advanced Driver Assistance System (ADAS) system, comprising:
an image sensor for generating image data from a scene;
an image recognition system coupled to receive said image data from said image sensor including a video recognition processor and a transceiver;
a processor block including a processor core coupled to said image recognition system, said processor core coupled to utilize at least one ECC memory circuit that includes ECC memory hardware and single port processor memory;
said ECC memory hardware comprising:
write path circuitry including write generation (Gen) ECC logic for generating first ECC bits from write data and for writing said first ECC bits and said write data to said processor memory;
read path circuitry including a check ECC block for coupling read data from said processor memory comprising read Gen ECC logic coupled to an XOR circuit that has an input for coupling to an ECC output of said processor memory, wherein an output of said XOR circuit provides a syndrome signal to a syndrome decode block coupled to a single bit error correction (SEC) block and for generating a multi-bit error detection (MED) interrupt signal;
a first multiplexer (MUX) having a first input for receiving said write data in series with an input to said write ECC generation logic or a second MUX having a first input for receiving said read data from said processor memory in series with an input of said read Gen ECC logic;
a cross-coupling connector for coupling said read data from said memory circuit to a second input of said first MUX or a cross-coupling connector for coupling said write data to a second input of said second MUX, and
an ECC bit comparator for comparing an output of said write Gen ECC logic to an output of said read Gen ECC logic.

9. The ADAS system of claim 8 , wherein an output of said comparator is coupled as an enable input to said syndrome decode block and as an enable input to said SEC block.

10. The ADAS system of claim 8 , wherein said ECC memory hardware and said processor memory are formed on a common substrate having at least a semiconductor surface.

11. The ADAS system of claim 8 , wherein said ECC memory hardware includes said first MUX and said second MUX.

12. The ADAS system of claim 8 , wherein said processor memory comprises a static random access memory (SRAM), read only memory (ROM), or a flash memory.

13. The ADAS system of claim 8 , wherein said ECC memory hardware and said processor memory are formed on a common substrate having at least a semiconductor surface.

14. The ADAS system of claim 13 , wherein common substrate and said semiconductor surface both comprise silicon.

15. The ADAS system of claim 8 , wherein said image sensor comprises a color camera.

Assignees

• Texas Instruments Inc

Inventors

• Jalan Saket
• Prathapan Indu
• Karkisaval Abhishek Ganapati

Classifications

• G06F3/064

  Management of blocks · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title