Multiprocessor programming toolkit for design reuse

Patent metadata

Field	Value
Publication number	US-9904542-B2
Application number	US-201314047135-A
Country	US
Kind code	B2
Filing date	Oct 7, 2013
Priority date	Nov 6, 2012
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

Techniques for specifying and implementing a software application targeted for execution on a multiprocessor array (MPA). The MPA may include a plurality of processing elements, supporting memory, and a high bandwidth interconnection network (IN), communicatively coupling the plurality of processing elements and supporting memory. In one embodiment, software code may include first program instructions executable to perform a function. In this embodiment, the software code may also include one or more language constructs that are configurable to specify one or more communication ports and one or more parameter inputs. In this embodiment, the one or more communication ports are configurable to specify communication with other software code. In this embodiment, the one or more parameter inputs are configurable to specify a set of hardware resources usable to execute the software code. In this embodiment, the hardware resources include multiple processors and may include multiple supporting memories.

First claim

What is claimed is:

1. A non-transitory computer-accessible memory medium that stores a library of software code deployable on a multiprocessor array (MPA), wherein the software code comprises:
a cell definition that includes:
first program instructions executable to perform a first function; and
one or more first language constructs which are user configurable to specify one or more communication ports and one or more parameter inputs;
wherein the one or more communication ports are user configurable to specify communication with other software code in a software application;
wherein the one or more parameter inputs are user configurable to specify a set of hardware resources usable to execute the software code, wherein the hardware resources include a plurality of processors and a plurality of memories; and

wherein multiple instances of the first program instructions specified by the cell definition are deployable, based on user input selecting the cell and specifying one or more different communication ports and one or more different parameter inputs for ones of the instances, in different hardware portions of at least one MPA to perform the first function in one or more software applications;
wherein each instance of the cell comprises a respective configuration of the one or more communication ports specifying connectivity of the one or more communication ports with other software code deployed on the MPA; and
wherein amounts of hardware resources in the respective hardware portion on which one or more respective instances of the cell are deployed are different and are based on the user-specified one or more parameter inputs.

2. The non-transitory computer-accessible memory medium of claim 1 ,
wherein a first instantiation of the cell is deployable on at least one MPA to perform the first function in a first software application, wherein the one or more communication ports have a first configuration specifying a first connectivity, and wherein the one or more parameter inputs specify a first set of hardware resources on the at least one MPA for deployment; and
wherein a second instantiation of the cell is deployable on at least one MPA to perform the first function in a second software application, wherein the one or more communication ports have a second configuration specifying a second connectivity, and wherein the one or more parameter inputs specify a second set of hardware resources on the at least one MPA for deployment.

3. The non-transitory computer-accessible memory medium of claim 2 , wherein the second instantiation of the cell utilizes more processors than the first instantiation of the software code based on configuration of the one or more parameter inputs.

4. The non-transitory computer-accessible memory medium of claim 2 , wherein second software application is a same software application as the first software application and wherein the first and second instantiations are configured to perform the first function in parallel.

5. The non-transitory computer-accessible memory medium of claim 1 wherein the one or more communication ports include one or more fabric ports and one or more shared memory ports.

6. The non-transitory computer-accessible memory medium of claim 1 , wherein the one or more parameter inputs are configurable to specify two or more of:
operation of the first function;
a data stream size;
a number of processors for deployment of the software code;
access to one or more general-purpose memories external to the MPA;
access to one or more MPA inputs and/or outputs;
an amount of data used to store temporary state when performing the first function; or
an amount of communication resources accessible to the software code.

7. The non-transitory computer-accessible memory medium of claim 1 ,
wherein one or more instances of the cell are deployable within a portion of the hardware resources on which another given instance of the cell is deployed and wherein communication ports of the one or more instances are configured to communicate via communications ports of the given instance.

8. The non-transitory computer-accessible memory medium of claim 1 , wherein the one or more parameter inputs are configurable during execution of the software code in order to adjust the set of hardware resources used to execute the software code.

9. A method for configuring a multiprocessor array (MPA), wherein the MPA comprises hardware resources including a plurality of processors and a plurality of memories, the method comprising:
storing a library of software code in a memory medium, wherein the software code includes a cell definition that includes: first program instructions executable to perform a first function, wherein the cell definition is usable in a first software application, wherein the cell definition comprises one or more first language constructs which specify communication connectivity of instances of the first program instructions specified by the cell definition with other code in the first software application, wherein the software code further comprises one or more second language constructs which specify a set of hardware resources for deployment of the cell; and
receiving user input creating multiple instances of the first program instructions specified by the cell definition for use in one or more applications, wherein said receiving user input creating the instances comprises:
receiving user input to the one or more first language constructs of different ones of the multiple instances specifying different communication connectivity; and
receiving user input to the one or more second language constructs specifying different amounts of hardware resources for respective ones of the multiple instances;

wherein the instances of the cell are deployable such that amounts of hardware resources in respective hardware portions on which the respective instances are deployed are different based on the user input to the second language constructs.

10. The method of claim 9 ;
wherein first and second instances of the software code are instantiated within another instance of software code.

11. The method of claim 9 , further comprising:
deploying the instances of the cell on a MPA using different amounts of processor and memory resources based on the user inputs to the second language constructs.

12. The method of claim 9 , further comprising:
adjusting a set of hardware resources on which an instance of a cell is deployed based on a change in input to the one or more second language constructs during execution of the software code.

13. The method of claim 9 , further comprising:
configuring one or more parameter inputs to alter operation of the first function.

14. A system, comprising:
one or more processors; and
one or more memories having program instructions stored thereon that are executable by cause operations comprising:
deploying software code on a multiprocessor array (MPA), wherein the software code comprises:
a cell definition that includes:
first program instructions executable to perform a first function; and
one or more first language constructs which are user configurable to specify one or more communication ports and one or more parameter inputs;
wherein the one or more communication ports are user configurable to specify communication with other software code in a software application;
wherein the one or more parameter inputs are user configurable to specify a set of hardware resources usable to execute the software code, wherein the hardware resources include a plurality of processors and a plurality of memories; and

wherein multiple instances of

Assignees

• Coherent Logix Inc

Inventors

• Lim Stephen E
• Ngo Viet N
• Nicholson Jeffrey M
• Beardslee John Mark
• Wang Teng I
• Shang Zhong Qing
• Purnell Michael Lyle

Classifications

• G06F8/71 Primary

  Version control (security arrangements therefor G06F21/57); Configuration management · CPC title

• G06F8/60

  Software deployment · CPC title

• G06F8/443

  Optimisation · CPC title

• G06F9/44505 Primary

  Configuring for program initiating, e.g. using registry, configuration files · CPC title