Methods and apparatus for performing floating point operations

Patent metadata

Field	Value
Publication number	US-9904512-B1
Application number	US-201313907134-A
Country	US
Kind code	B1
Filing date	May 31, 2013
Priority date	May 31, 2013
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A floating-point arithmetic block for performing arithmetic operations on floating-point numbers on an integrated circuit includes a unit to handle exceptions, a unit to handle the exponent, a unit for normalization and rounding, and a core having a multiplier, a subtractor, storage circuitry to store multiple initial mantissa values, and configurable interconnect circuitry. The configurable interconnect circuitry may be configured to route signals throughout the floating-point arithmetic block. The configuration may be performed by a finite state machine that controls the configurable interconnect depending on the selected floating-point arithmetic operation. The floating-point arithmetic block may be configured to implement a variety of floating-point arithmetic operations including the inverse square root operation, the square root operation, the inverse operation, the division, the multiplication, the addition, and the subtraction.

First claim

What is claimed is:

1. Circuitry for performing arithmetic operations on floating-point numbers each having an exponent and a mantissa, comprising:
an input;
a multiplier circuit coupled to the input;
a right shifter coupled to the multiplier circuit;
a subtractor circuit coupled to the multiplier circuit;
a storage circuit coupled to the multiplier circuit and the subtractor circuit, wherein the storage circuit stores a plurality of initial mantissa values; and
configurable interconnect circuitry operable to convey signals among the input, the multiplier circuit, the subtractor circuit, and the storage circuit, wherein the configurable interconnect circuitry is configurable to implement approximations for a plurality of arithmetic operations.

2. The circuitry of claim 1 , wherein:
the multiplier circuit comprises a fixed-point multiplier; and
the subtractor circuit comprises a fixed-point subtractor.

3. The circuitry of claim 1 , wherein the configurable interconnect circuitry is configurable to implement approximations for arithmetic operations selected from the group consisting of: inverse square root, square root, inverse, division, multiplication, addition, and subtraction operations.

4. The circuitry of claim 1 , wherein the configurable interconnect circuitry comprises a multiplexer having inputs coupled to the right shifter and the multiplier circuit, and an output coupled to the subtractor circuit, wherein the multiplexer selects between the signals generated from the multiplier circuit and the signals generated from the right shifter, and wherein the configurable interconnect circuitry routes the selected signals from the multiplexer to the subtractor circuit.

5. The circuitry of claim 4 , wherein the configurable interconnect circuitry comprises a register coupled between the multiplexer and the subtractor circuit.

6. The circuitry of claim 1 further comprising:
a left shifter coupled to the storage circuit.

7. The circuitry of claim 6 further comprising:
an additional left shifter coupled to the multiplier circuit and the subtractor circuit.

8. The circuitry of claim 7 , wherein the configurable interconnect circuitry comprises a multiplexer having inputs coupled to the left shifter, the additional left shifter, and an additonal storage circuit storing a constant number, and an output coupled to the subtractor circuit, wherenin the mulitplexer selects among the signals received from the additional storage circuit, the signals generated from the left shifter, and the signals generated from the additional left shifter, and wherein configurable interconnect circuitry routes the selected signals from the multiplexer to the subtractor circuit.

9. The circuitry of claim 1 , wherein the configurable interconnect circuitry comprises a multiplexer having inputs coupled to the input, the multiplier circuit, the subtractor circuit, and the storage circuit, and an output coupled to the multiplier circuit, wherein the multiplexer selects among the signals received from the input, the signals generated from the multiplier circuit, the signals generated from the subtractor circuit, and the signals generated from the storage circuit, and wherein the configurable interconnect circuitry routes the selected signals from the multiplexer to the multiplier circuit.

10. A method for performing a plurality of floating-point operations on an integrated circuit, comprising:
receiving, at a control circuit, a control signal specifying a floating-point operation from the plurality of floating-point operations;
at the control circuit, implementing a state machine that is associated with the floating-point operation specified by the control signal and using the state machine to direct arithmetic circuitry on the integrated circuit;
receiving at least one floating-point number having an exponent and a mantissa;
retrieving an initial approximation value for a mantissa result from a storage circuit based on the specified floating-point operation;
with the arithmetic circuitry on the integrated circuit, computing a resulting exponent of the specified floating-point operation based on the exponent of the at least one floating-point number and the mantissa of the at least one floating-point number;
with an additional arithmetic circuitry on the integrated circuit, computing an approximation for the mantissa result of the specified floating-point operation based on the initial approximation value by:
receiving the mantissa of the at least one floating-point number at multiplier circuitry in the additional arithmetic circuitry;
routing the output of the multiplier circuitry to a right shifter in the additional arithmetic circuitry; and
at the right shifter in the additional arithmetic circuitry, right shifting the output of the multiplier circuitry by one bit position.

11. The method of claim 10 , wherein the arithmetic circuitry includes configurable interconnect resources, the method further comprising:
generating control signals to configure the configurable interconnect resources based on the specified floating-point opereation.

12. The method of claim 10 , wherein the additional arithmetic circuitry includes configurable interconnect resources, further comprising:
generating control signals to select a configuration for the configurable interconnect resources based on specified floating-point operation.

13. A method for perfroming a floating-point operation with a floating-point number on an integrated circuit, comprising:
receiving a mantissa of the floating-point number;
retrieving an initial approximation value from a storage circuit;
with arithmetic circuitry on the integrated circuit, computing an approximation of a mantissa result of the floating point operation based on the initial approximation value by receiving the initial approximation value at a multiplier circuit and at a left shifter circuit;
at the multiplier circuit, generating a first product by multiplying the initial approximation value with itself;
at the left shifter circuit, left shifting the initial approximation value by one bit position; and
with the arithmetic circuitry, computing an exponent result of the floating point operation based on the floating-point number.

14. The method of claim 13 , wherein the floating-point operation comprises an inverse of the mantissa of the floating-point number, and wherein computing the approximation of the mantissa result of the floating point operation based on the initial approximation value comprises computing the approximation of the inverse of the mantissa, wherein computing the approximation of the inverse of the mantissa further comprises:
with the left shifter, generating a left shifted approximation value of the initial approximation value by shifting the initial approximation value one bit to the left.

15. The method of claim 14 , wherein computing the approximation further comprises:
receiving the first product and the mantissa at the multiplier; and
with the multiplier, generating a second product by multiplying the first product and the mantissa.

16. The method of claim 15 , wherein computing the approximation further comprises:
receiving the second product and the left shifted approximation value at a subtractor;
with the subtractor, generating a difference of the left shifted approximation value and the second product; and
providing the difference at an output of the arithmetic circuitry.

17. The method of claim 16 , wherein computing the approximation further comprises:
computing a second approximation of the inverse of

Assignees

• Altera Corp

Inventors

• Pasca Bogdan

Classifications

• G06F7/483 Primary

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title