Apparatus, system, and method for reducing a number of intersymbol interference components to be suppressed

Patent metadata

Field	Value
Publication number	US-9900121-B1
Application number	US-201615260117-A
Country	US
Kind code	B1
Filing date	Sep 8, 2016
Priority date	Sep 8, 2016
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

An apparatus, system, and method are provided for reducing a number of intersymbol interference components to be suppressed. Included is a receiver path with a linear equalizer configured to: receive a signal pulse including a data component and a first number of post-cursor intersymbol interference components, delay and process the signal pulse such that the signal pulse includes a second number of post-cursor intersymbol interference components which is less than the first number of post-cursor intersymbol interference components, and produce an output signal that includes the data component and the second number of post-cursor intersymbol interference components. The receiver path further includes a decision feedback equalizer in electrical communication with the linear equalizer. The decision feedback equalizer is configured to: receive the output signal from the linear equalizer, and suppress the second number of the post-cursor intersymbol interference components of the output signal.

First claim

What is claimed is:

1. An apparatus, comprising:
a linear equalizer that includes:
a delay circuit including a plurality of delay components,
a controller in electrical communication with the delay circuit,
a network of multipliers in electrical communication with the delay circuit, wherein each multiplier in the network of multipliers is associated with a coefficient, and
an adder in electrical communication with the network of multipliers, wherein the adder is configured to generate an output signal,
wherein the controller is configured, during calibration of the linear equalizer, to adjust a length of delay exhibited by a first delay component of the plurality of delay components such that a magnitude of a first post-cursor intersymbol interference component in the output signal is suppressed below a threshold value; and

a decision feedback equalizer in electrical communication with the linear equalizer, the decision feedback equalizer configured to:
receive the output signal from the linear equalizer, and
suppress a number of post-cursor intersymbol interference components of the output signal, wherein the number of post-cursor intersymbol interference components does not include the first post-cursor intersymbol interference component.

2. The apparatus of claim 1 , wherein the linear equalizer and decision feedback equalizer are included in a receiver path of a serializer/deserializer.

3. The apparatus of claim 1 , wherein the linear equalizer includes a feed forward equalizer.

4. The apparatus of claim 1 , wherein the decision feedback equalizer includes at least one comparator and at least one latch in electrical communication with a decoder.

5. The apparatus of claim 4 , wherein the decision feedback equalizer further includes a tapped delay line in electrical communication with an adder, and wherein an output of the decoder is fed back to the adder via the tapped delay line.

6. The apparatus of claim 1 , wherein the threshold value is 10% of a signal pulse magnitude.

7. The apparatus of claim 1 , wherein at least a portion of the decision feedback equalizer is configured for operating at a rate that is a fraction of an operational speed of the apparatus such that one or more downstream components has sufficient time to operate.

8. The apparatus of claim 1 , wherein the decision feedback equalizer includes a plurality of decision feedback equalizer components that operate using different clocks.

9. The apparatus of claim 1 , wherein the controller is configured, during calibration of the linear equalizer, to adjust a length of delay exhibited by a second delay component of the plurality of delay components such that a magnitude of a first pre-cursor intersymbol interference component in the output signal is suppressed below a threshold value.

10. The apparatus of claim 1 , wherein a magnitude of the first post-cursor intersymbol interference component in the output signal is suppressed to zero.

11. The apparatus of claim 1 , wherein the decision feedback equalizer includes a pair of decision feedback equalizer (DFE) components including an even DFE component and an odd DFE component.

12. The apparatus of claim 11 , wherein each DFE component in the pair of DFE components includes a plurality of comparators in electrical communication with a decoder and an amplifier array in electrical communication with a flip-flop array, wherein each amplifier in the amplifier array receives a signal from a different tap point of the flip-flop array, each tap point corresponding to a particular post-cursor intersymbol interference component in the number of post-cursor intersymbol interference components.

13. A method, comprising:
receiving, at an input of a linear equalizer, a signal pulse, wherein the linear equalizer includes:
a delay circuit including a plurality of delay components,
a controller in electrical communication with the delay circuit and configured to adjust a length of delay exhibited by each delay component in the plurality of delay components,
a network of multipliers in electrical communication with the delay circuit, wherein each multiplier in the network of multipliers is associated with a coefficient, and
an adder in electrical communication with the network of multipliers, wherein the adder is configured to generate an output signal,
wherein the controller is configured, during calibration of the linear equalizer, to adjust a length of delay exhibited by a first delay component of the plurality of delay components such that a magnitude of a first post-cursor intersymbol interference component in the output signal is suppressed below a threshold value;

receiving the output signal at a decision feedback equalizer in electrical communication with the linear equalizer; and
suppressing a number of the post-cursor intersymbol interference components of the output signal, utilizing the decision feedback equalizer, wherein the number of post-cursor intersymbol interference components does not include the first post-cursor intersymbol interference component.

14. The method of claim 13 , wherein the linear equalizer includes a feed forward equalizer.

15. The method of claim 13 , further comprising latching the output signal received by the decision feedback equalizer to generate a latched signal.

16. The method of claim 15 , further comprising decoding the latched signal.

17. The method of claim 13 , wherein the threshold value is 10% of a signal pulse magnitude.

18. The method of claim 13 , wherein the controller is configured, during calibration of the linear equalizer, to adjust a length of delay exhibited by a second delay component of the plurality of delay components such that a magnitude of a first pre-cursor intersymbol interference component in the output signal is suppressed below a threshold value.

19. The method of claim 13 , wherein a magnitude of the first post-cursor intersymbol interference component in the output signal is suppressed to zero.

20. The method of claim 13 , wherein the decision feedback equalizer includes a pair of decision feedback equalizer (DFE) components including an even DFE component and an odd DFE component.

21. The method of claim 20 , wherein each DFE component in the pair of DFE components includes a plurality of comparators in electrical communication with a decoder and an amplifier array in electrical communication with a flip-flop array, wherein each amplifier in the amplifier array receives a signal from a different tap point of the flip-flop array, each tap point corresponding to a particular post-cursor intersymbol interference component in the number of post-cursor intersymbol interference components.

Assignees

• Futurewei Technologies Inc

Inventors

• Takatori Hiroshi

Classifications

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L43/16

  Threshold monitoring · CPC title

• H04J11/0036 Primary

  at the receiver · CPC title

• H04L1/00

  Arrangements for detecting or preventing errors in the information received {(correcting synchronisation H04L7/00)} · CPC title