Adaptive serdes receiver

Patent metadata

Field	Value
Publication number	US-9565037-B1
Application number	US-201514977122-A
Country	US
Kind code	B1
Filing date	Dec 21, 2015
Priority date	Dec 21, 2015
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

One embodiment provides an apparatus. The apparatus includes a feedforward equalizer (FFE), an FFE data slicer and an FFE least mean square (LMS) module. The FFE data slicer is to threshold detect a sample of a received analog training signal, a result of the threshold detecting corresponding to an input signal digital decision. The FFE LMS module is to determine a plurality of FFE coefficients based, at least in part, on an output of the FFE data slicer and based, at least in part, on a mean square error corresponding to a difference between an equalized sample and a reference.

First claim

What is claimed is:

1. An apparatus comprising:
a feedforward equalizer (FFE);
an FFE data slicer to threshold detect a sample of a received analog training signal, a result of the threshold detecting corresponding to an input signal digital decision; and
FFE least mean square (LMS) circuitry to determine a plurality of FFE coefficients based, at least in part, on an output of the FFE data slicer and based, at least in part, on a mean square error corresponding to a difference between an equalized sample and a reference;
wherein the output of the FFE data slicer comprises three sequential input signal digital decisions separated in time by a delay, D, and the FFE LMS circuitry is to determine three FFE coefficients based, at least in part, on the three sequential input signal digital decisions.

2. The apparatus of claim 1 , wherein the FFE comprises a plurality of delay blocks, three multipliers and a summing junction, each multiplier to receive a respective FFE coefficient and a respective sample of the received analog training signal.

3. The apparatus of claim 1 , wherein each of the plurality of FFE coefficients is determined using a gradient descent technique.

4. The apparatus of claim 1 , wherein the FFE is to equalize a received analog data signal utilizing the plurality of FFE coefficients.

5. A method comprising:
threshold detecting, by a feedforward equalizer (FFE) data slicer, a sample of a received analog training signal, a result of the threshold detecting corresponding to an input signal digital decision, the received analog training signal input to an FFE;
determining, by FFE least mean square (LMS) circuitry, a plurality of FFE coefficients based, at least in part, on an output of the FFE data slicer and based, at least in part, on a mean square error corresponding to a difference between an equalized sample and a reference; and
determining, by the FFE LMS circuitry, three FFE coefficients based, at least in part, on three sequential input signal digital decisions, the output of the FFE data slicer comprising the three sequential input signal digital decisions, adjacent in time input signal digital decisions separated in time by a delay, D.

6. The method of claim 5 , further comprising threshold detecting, by a DFE data slicer, a sample of an output of a decision feedback equalizer (DFE), the DFE coupled to an output of the FFE, a result of the detecting corresponding to a digital output.

7. The method of claim 6 , further comprising:
determining, by DFE LMS circuitry, a plurality of DFE coefficients based, at least in part, on the mean square error and based, at least in part, on a plurality of prior digital outputs.

8. The method of claim 5 , wherein the FFE comprises a plurality of delay blocks, three multipliers and a summing junction, further comprising receiving, by each multiplier, a respective FFE coefficient and a respective sample of the received analog training signal.

9. The method of claim 5 , wherein each of the plurality of FFE coefficients is determined using a gradient descent technique.

10. The method of claim 7 , wherein the plurality of FFE coefficients are determined after the plurality of DFE coefficients are determined.

11. The method of claim 10 , wherein each of the plurality of DFE coefficients is updated after determining the plurality of FFE coefficients.

12. The method of claim 5 , further comprising equalizing, by an FFE, a received analog data signal using the plurality of FFE coefficients.

13. A receiver comprising:
a feedforward equalizer (FFE);
a decision feedback equalizer (DFE) coupled to an output of the FFE;
a DFE data slicer coupled to an output of the DFE; and
adaptation logic comprising:
an FFE data slicer to threshold detect a sample of a received analog training signal, a result of the threshold detecting corresponding to an input signal digital decision, and
FFE least mean square (LMS) circuitry to determine a plurality of FFE coefficients based, at least in part, on an output of the FFE data slicer and based, at least in part, on a mean square error corresponding to a difference between an equalized sample and a reference;
wherein the output of the FFE data slicer comprises three sequential input signal digital decisions separated in time by a delay, D, and the FFE LMS circuitry module is to determine three FFE coefficients based, at least in part, on the three sequential input signal digital decisions.

14. The receiver of claim 13 , wherein the DFE data slicer is to threshold detect a sample of an output of the DFE, a result of the detecting corresponding to a digital output.

15. The receiver of claim 13 , wherein the adaptation logic further comprises DFE LMS circuitry to determine a plurality of DFE coefficients based, at least in part, on the mean square error and based, at least in part, on a plurality of prior digital outputs.

16. The receiver of claim 13 , wherein the FFE comprises a plurality of delay blocks, three multipliers and a summing junction, each multiplier to receive a respective FFE coefficient and a respective sample of the received analog training signal.

17. The receiver of claim 13 , wherein each of the plurality of FFE coefficients is determined using a gradient descent technique.

18. The receiver of claim 15 , wherein the plurality of FFE coefficients are determined after the plurality of DFE coefficients are determined.

19. The receiver of claim 18 , wherein each of the plurality of DFE coefficients is updated after determining the plurality of FFE coefficients.

Assignees

• Intel Corp

Inventors

• Liu Zao
• Bermensolo Todd L

Classifications

• H04L25/03057 Primary

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L2025/03636

  Algorithms using least mean square [LMS] · CPC title