Method of forming semiconductor device with different energy gap oxide semiconductor stacked layers

Patent metadata

Field	Value
Publication number	US-9899536-B2
Application number	US-201715648914-A
Country	US
Kind code	B2
Filing date	Jul 13, 2017
Priority date	May 31, 2012
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A highly reliable semiconductor device including an oxide semiconductor is provided by preventing a change in its electrical characteristics. A semiconductor device which includes a first oxide semiconductor layer which is in contact with a source electrode layer and a drain electrode layer and a second oxide semiconductor layer which serves as a main current path (channel) of a transistor is provided. The first oxide semiconductor layer serves as a buffer layer for preventing a constituent element of the source and drain electrode layers from diffusing into the channel. By providing the first oxide semiconductor layer, it is possible to prevent diffusion of the constituent element into an interface between the first oxide semiconductor layer and the second oxide semiconductor layer and into the second oxide semiconductor layer.

First claim

The invention claimed is:

1. A method for manufacturing a semiconductor device comprising the steps of:
forming a gate electrode layer;
forming a first gate insulating layer using a first mixed gas comprising a gas containing silicon and a gas comprising nitrogen;
forming a second gate insulating layer using a second mixed gas comprising a gas containing silicon and a gas containing dinitrogen monoxide;
forming a first oxide semiconductor layer over the second gate insulating layer;
forming a second oxide semiconductor layer over the first oxide semiconductor layer;
forming a source electrode layer over the second oxide semiconductor layer; and
forming a drain electrode layer over the second oxide semiconductor layer,
wherein the first oxide semiconductor layer comprises one or more of indium, gallium, and zinc,
wherein the second oxide semiconductor layer comprises one or more of indium, gallium, and zinc, and
wherein an energy gap of the second oxide semiconductor layer is larger than an energy gap of the first oxide semiconductor layer.

2. The method for manufacturing the semiconductor device according to claim 1 , further comprising the step of supplying a third mixed gas comprising a gas containing silicon, a gas containing nitrogen, and a gas containing ammonia after supplying the first mixed gas to form the first gate insulating layer.

3. The method for manufacturing the semiconductor device according to claim 2 , further comprising the step of supplying a fourth mixed gas comprising a gas containing silicon and a gas comprising nitrogen after supplying the third mixed gas to form the first gate insulating layer.

4. The method for manufacturing the semiconductor device according to claim 1 , wherein each of the first gate insulating layer and the second gate insulating layer is formed by a plasma CVD.

5. The method for manufacturing the semiconductor device according to claim 1 , wherein the first gate insulating layer includes a silicon nitride film.

6. The method for manufacturing the semiconductor device according to claim 1 , wherein the second oxide semiconductor layer is a crystalline oxide semiconductor layer.

7. The method for manufacturing the semiconductor device according to claim 1 ,
wherein a content of the indium is higher than a content of the gallium in the first oxide semiconductor layer, and
wherein a content of the indium is lower than or equal to a content of the gallium in the second oxide semiconductor layer.

8. A method for manufacturing a semiconductor device comprising the steps of:
forming a gate electrode layer;
forming a first gate insulating layer using a first mixed gas comprising a gas containing silicon and a gas comprising nitrogen;
forming a second gate insulating layer using a second mixed gas comprising a gas containing silicon and a gas containing dinitrogen monoxide;
forming a first oxide semiconductor layer over the second gate insulating layer;
forming a second oxide semiconductor layer over the first oxide semiconductor layer;
forming a source electrode layer over the second oxide semiconductor layer; and
forming a drain electrode layer over the second oxide semiconductor layer,
wherein the first oxide semiconductor layer comprises one or more of indium, gallium, and zinc,
wherein the second oxide semiconductor layer comprises one or more of indium, gallium, and zinc,
wherein an energy gap of the second oxide semiconductor layer is larger than an energy gap of the first oxide semiconductor layer, and
wherein each of the source electrode layer and the drain electrode layer comprises copper.

9. The method for manufacturing the semiconductor device according to claim 8 , further comprising the step of supplying a third mixed gas comprising a gas containing silicon, a gas containing nitrogen, and a gas containing ammonia after supplying the first mixed gas to form the first gate insulating layer.

10. The method for manufacturing the semiconductor device according to claim 9 , further comprising the step of supplying a fourth mixed gas comprising a gas containing silicon and a gas comprising nitrogen after supplying the third mixed gas to form the first gate insulating layer.

11. The method for manufacturing the semiconductor device according to claim 8 , wherein each of the first gate insulating layer and the second gate insulating layer is formed by a plasma CVD.

12. The method for manufacturing the semiconductor device according to claim 8 , wherein the first gate insulating layer includes a silicon nitride film.

13. The method for manufacturing the semiconductor device according to claim 8 , wherein the second oxide semiconductor layer is a crystalline oxide semiconductor layer.

14. The method for manufacturing the semiconductor device according to claim 8 ,
wherein a content of the indium is higher than a content of the gallium in the first oxide semiconductor layer, and
wherein a content of the indium is lower than or equal to a content of the gallium in the second oxide semiconductor layer.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Koezuka Junichi
• Shima Yukinori
• Tokunaga Hajime

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title

• H01L29/518

  Electricity · mapped topic

• H01L29/513

  Electricity · mapped topic