Method to make self-aligned vertical field effect transistor

Patent metadata

Field	Value
Publication number	US-9899529-B2
Application number	US-201615195886-A
Country	US
Kind code	B2
Filing date	Jun 28, 2016
Priority date	Nov 9, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A method for making a self-aligned vertical nanosheet field effect transistor. A vertical trench is etched in a layered structure including a plurality of layers, using reactive ion etching, and filled, using an epitaxial process, with a vertical semiconductor nanosheet. A sacrificial layer from among the plurality of layers is etched out and replaced with a conductive (e.g., metal) gate layer coated with a high-dielectric-constant dielectric material. Two other layers from among the plurality of layers, one above and one below the gate layer, are doped, and act as dopant donors for a diffusion process that forms two PN junctions in the vertical semiconductor nanosheet.

First claim

What is claimed is:

1. A method for fabricating a field effect transistor having a channel and a gate, the method comprising:
depositing a plurality of layers, including a sacrificial layer, on a substrate;
etching a first trench through the plurality of layers;
growing a vertical semiconductor sheet, to form the channel, in the first trench;
etching the sacrificial layer to form a first gap; and
forming a conductive layer in the first gap, to form the gate,
wherein the growing comprises completely filling the first trench.

2. The method of claim 1 , wherein the sacrificial layer comprises, as a major component, silicon nitride.

3. The method of claim 1 , wherein the plurality of layers further comprises:
two amorphous carbon layers;
two layers of undoped oxide; and
two layers of doped oxide.

4. The method of claim 3 , wherein the plurality of layers comprises, in order, from the substrate:
a first amorphous carbon layer of the two amorphous carbon layers;
a first layer of doped oxide of the two layers of doped oxide;
a first layer of undoped oxide of the two layers of undoped oxide;
the sacrificial layer, comprising, as a major component, silicon nitride;
a second layer of undoped oxide of the two layers of undoped oxide;
a second layer of doped oxide of the two layers of doped oxide; and
a second amorphous carbon layer of the two amorphous carbon layers.

5. A method for fabricating a field effect transistor having a channel and a gate, the method comprising:
depositing a plurality of layers, including a sacrificial layer, on a substrate;
etching a first trench through the plurality of layers;
growing a vertical semiconductor sheet, to form the channel, in the first trench;
etching the sacrificial layer to form a first gap; and
forming a conductive layer in the first gap, to form the gate,
wherein the plurality of layers further comprises:
two amorphous carbon layers;
two layers of undoped oxide; and
two layers of doped oxide,

wherein the growing of the vertical semiconductor sheet, to form the channel, in the first trench, comprises:
growing the vertical semiconductor sheet to include a first dopant at a lower end of the vertical semiconductor sheet; and
growing the vertical semiconductor sheet to include the first dopant at an upper end of the vertical semiconductor sheet.

6. The method of claim 5 , wherein:
the growing of the vertical semiconductor sheet, to form the channel, in the first trench produces an intermediate structure, and
each of the layers of doped oxide includes a second dopant,
the method further comprising:
heating the intermediate structure to cause the second dopant to diffuse out of the layers of doped oxide and into the vertical semiconductor sheet.

7. The method of claim 6 , wherein:
the inclusion of the first dopant results in the lower end having a first conductivity type and the upper end of the vertical semiconductor sheet having the first conductivity type, and
the second dopant is selected to produce, when diffused into the vertical semiconductor sheet, a semiconductor material of the first conductivity type.

8. The method of claim 7 , the thickness of the first and second layer of undoped oxide being the same, and chosen to provide a desired separation of the second dopants diffused into the vertical semiconductor sheet.

9. The method of claim 3 , wherein the growing of the vertical semiconductor sheet, to form the channel, in the first trench produces an intermediate structure, the vertical semiconductor sheet extending above an upper surface of an upper one of the two amorphous carbon layers.

10. The method of claim 9 , further comprising, after the growing of the vertical semiconductor sheet, to form the channel, in the first trench, and before the etching of the sacrificial layer to form the first gap:
planarizing an upper surface of the intermediate structure utilizing chemical mechanical planarization (CMP).

11. A method for fabricating a field effect transistor having a channel and a gate, the method comprising:
depositing a plurality of layers, including a sacrificial layer, on a substrate;
etching a first trench through the plurality of layers;
growing a vertical semiconductor sheet, to form the channel, in the first trench;
etching the sacrificial layer to form a first gap; and
forming a conductive layer in the first gap, to form the gate,
wherein the plurality of layers further comprises:
two amorphous carbon layers;
two layers of undoped oxide; and
two layers of doped oxide,

the method further comprising, after the forming of the conductive layer in the first gap, to form the gate:
etching a lower one of the two amorphous carbon layers to form a second gap;
etching an upper one of the two amorphous carbon layers to form a third gap;
forming a lower contact layer in the second gap; and
forming an upper contact layer in the third gap.

12. The method of claim 11 , further comprising:
after the etching of the first trench through the plurality of layers, and before the growing of the vertical semiconductor sheet, to form the channel, in the first trench:
depositing a liner of oxide; and

after the etching of the lower one of the two amorphous carbon layers to form the second gap and the etching of the upper one of the two amorphous carbon layers to form the third gap, and before the forming of the lower contact layer in the second gap and the forming of the upper contact layer in the third gap:
etching the liner of oxide within the second gap and within the third gap.

13. The method of claim 3 , further comprising, after the growing of the vertical semiconductor sheet, to form the channel, in the first trench, and before the forming of the conductive layer in the first gap, to form the gate:
etching a lower one of the two amorphous carbon layers to form a second gap;
etching an upper one of the two amorphous carbon layers to form a third gap;
forming a lower contact layer in the second gap; and
forming an upper contact layer in the third gap.

14. The method of claim 13 , further comprising:
after the etching of the first trench through the plurality of layers, and before the growing of the vertical semiconductor sheet, to form the channel, in the first trench:
depositing a liner of oxide; and

after the etching of the lower one of the two amorphous carbon layers to form the second gap and the etching of the upper one of the two amorphous carbon layers to form the third gap, and before the forming of the lower contact layer in the second gap and the forming of the upper contact layer in the third gap:
etching the liner of oxide within the second gap and within the third gap.

15. The method of claim 1 , further comprising, after the etching of the sacrificial layer to form the first gap; and before the forming of the conductive layer in the first gap, to form the gate:
forming a dielectric layer on the surfaces of the first gap.

16. The method of claim 1 , further comprising, after the etching of the first trench through the plurality of layers, and before the growing of the vertical semiconductor sheet, to form the channel, in the first trench:
depositing a liner of oxide.

17. The method of claim 16 , further comprising, after the depositing of the liner of oxide, and before the growing of the vertical semiconductor sheet, to form the channel, in the first trench:
removing horizontal portions of the liner of oxide using a reactive ion etch process.

18. The method of claim 1 , wherein the growing of the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Joon Goo
• Obradovic Borna
• Rodder Mark

Classifications

• H10P32/1412

  through the applied layer · CPC title

• H10P32/171

  being group IV material · CPC title

• H01L29/42392

  Electricity · mapped topic

• H01L29/78654

  Electricity · mapped topic

• H01L29/78642 Primary

  Electricity · mapped topic