Dislocation stress memorization technique (DSMT) on epitaxial channel devices

Patent metadata

Field	Value
Publication number	US-9419136-B2
Application number	US-201414252147-A
Country	US
Kind code	B2
Filing date	Apr 14, 2014
Priority date	Apr 14, 2014
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to an epitaxial channel region, and an associated method of formation. The transistor device has an epitaxial stack disposed over a semiconductor substrate, and a gate structure disposed over the epitaxial stack. A channel region extends below the gate structure between epitaxial source and drain regions located on opposing sides of the gate structure. First and second dislocation stress memorization (DSM) regions have a stressed lattice that generates stress within the channel region. The first and second DSM regions respectively extend from below the epitaxial source region to a first location within the epitaxial source region from below the epitaxial drain region to a second location within the epitaxial drain region. Using the first and second DSM regions to stress the channel region, improves device performance.

First claim

What is claimed is:

1. A transistor device, comprising:
an epitaxial stack disposed over a semiconductor substrate and having a first epitaxial layer and an overlying second epitaxial layer;
a gate structure disposed over the epitaxial stack;
a channel region extending below the gate structure between an epitaxial source region and an epitaxial drain region, which are disposed within the epitaxial stack and the semiconductor substrate on opposing sides of the gate structure; and
first and second dislocation stress memorization (DSM) regions, which comprise stressed lattices configured to generate stress within the channel region, respectively extending from below the epitaxial source region to a first location within the epitaxial source region and from below the epitaxial drain region to a second location within the epitaxial drain region.

2. The transistor device of claim 1 , wherein a height of the epitaxial stack is less than a height of the first and second dislocation stress memorization (DSM) regions.

3. The transistor device of claim 1 , wherein the first and second DSM regions are laterally separated from sidewall spacers of the gate structure by a non-zero distance.

4. The transistor device of claim 3 , wherein the first and second DSM regions are laterally separated from the gate structure by a distance of less than approximately 10 nm.

5. The transistor device of claim 1 , further comprising:
a recessed source contact extending from a top surface of the epitaxial source region to a position within the first DSM region underlying the to surface of the epitaxial source region; and
a recessed drain contact extending from a top surface of the epitaxial drain region to a position within the second DSM region underlying the to surface of the epitaxial drain region.

6. The transistor device of claim 1 , wherein the epitaxial source region and the epitaxial drain region comprise silicon phosphate (SiP).

7. The transistor device of claim 1 , wherein the epitaxial stack comprises:
a silicon carbon epitaxial layer in contact with an underlying semiconductor material of the semiconductor substrate; and
a lightly doped silicon epitaxial layer disposed over the silicon carbon layer.

8. A transistor device, comprising:
an epitaxial stack having a silicon carbon epitaxial layer disposed over a semiconductor substrate, and a lightly doped silicon epitaxial layer disposed over the silicon carbon layer;
a gate structure disposed over the lightly doped silicon epitaxial layer;
a channel region extending below the gate structure between an epitaxial source region and an epitaxial drain region, which are disposed within the epitaxial stack and the semiconductor substrate on opposing sides of the gate structure; and
first and second dislocation stress memorization (DSM) regions, which comprise materials of the epitaxial source and drain regions and the semiconductor substrate having a stressed lattice configured to generate stress within the channel region, respectively extending from below the epitaxial source region to a first location within the epitaxial source region from below the epitaxial drain region to a second location within the epitaxial drain region.

9. The transistor device of claim 8 , wherein the first and second DSM regions are laterally separated from sidewall spacers of the gate structure by a non-zero distance.

10. The transistor device of claim 8 , further comprising:
a recessed source contact extending from a top surface of the epitaxial source region to a position within the first DSM region underlying the to surface of the epitaxial source region; and
a recessed drain contact extending from a top surface of the epitaxial drain region to a position within the second DSM region underlying the to surface of the epitaxial drain region.

11. The transistor device of claim 8 , wherein the first and second DSM regions respectively extend to a distance of approximately 2 nm below the epitaxial source region and the epitaxial drain region.

12. The transistor device of claim 8 , wherein the epitaxial source region and the epitaxial drain region comprise silicon phosphate (SiP).

13. The transistor device of claim 8 , wherein the silicon carbon epitaxial layer has a carbon content of approximately 1%.

14. A transistor device, comprising:
a first epitaxial layer disposed over a semiconductor substrate;
a second epitaxial layer disposed over the first epitaxial layer;
a first dislocation stress memorization (DSM) region comprising a re-crystallized amorphous material extending from the semiconductor substrate to a first location within an epitaxial source region within the second epitaxial layer;
a second DSM region comprising the re-crystallized amorphous material extending from within the semiconductor substrate to a second location within an epitaxial drain region within the second epitaxial layer; and
a gate structure disposed over the second epitaxial layer at a position laterally arranged between the first and second DSM regions.

15. The transistor device of claim 14 , wherein the re-crystallized amorphous material comprises stacking defects along a (111) plane.

16. The transistor device of claim 14 , wherein the epitaxial source region extends from within the semiconductor substrate to a first position overlying the silicon layer and the epitaxial drain region extends from within the semiconductor substrate to a second position overlying the second epitaxial layer.

17. The transistor device of claim 14 , wherein a sum of heights of the first epitaxial layer and the second epitaxial layer is less than a height of the first DSM region or the second DSM region.

18. The transistor device of claim 1 , wherein the first and second DSM regions have a smaller width that the epitaxial source and drain regions.

19. The transistor device of claim 7 , wherein the first and second DSM regions vertically extend through the silicon carbon epitaxial layer.

20. The transistor device of claim 8 , wherein the first and second DSM regions have a smaller width that the epitaxial source and drain regions.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Yu Tsung-Hsing
• Huang Shih-Syuan
• Sheu Yi-Ming
• Goto Ken-Ichi

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/226

  at a temperature lower than room temperature · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D30/791 Primary

  Arrangements for exerting mechanical stress on the crystal lattice of the channel regions · CPC title