Two-dimensional material semiconductor device

Patent metadata

Field	Value
Publication number	US-9899501-B2
Application number	US-201615380887-A
Country	US
Kind code	B2
Filing date	Dec 15, 2016
Priority date	Dec 22, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a two-dimensional material layer having a longitudinal direction, the two-dimensional material layer comprising a channel region, and at opposite sides of the channel region, a source region at one side in a longitudinal direction of the two-dimensional material layer and a drain region at an other side in the longitudinal direction of the two-dimensional material layer;
a first gate stack and a second gate stack in contact with the two-dimensional material layer, the first and second gate stack being spaced apart over a distance; wherein the first gate stack and the second gate stack each comprise a gate dielectric layer and a gate electrode, the gate dielectric layer being sandwiched between the gate electrode and the two-dimensional material layer, wherein the first gate stack is located on the channel region of the two-dimensional material layer and in between the source region and the second gate stack, wherein the first gate stack is configured to control injection of carriers from the source region to the channel region, wherein the second gate stack is located on the channel region of the two-dimensional material layer, and wherein the second gate stack is configured to control conduction of the channel region.

2. The semiconductor device of claim 1 , wherein the first gate stack configured to control the injection of carriers forms discrete energy levels and a region of depleted density of states either in a conduction band or in a valence band of the two-dimensional material layer underneath the first gate stack upon application of a first voltage to the first gate stack at a source-to-drain voltage and a second voltage to the second gate stack.

3. The semiconductor device of claim 2 , configured such that upon applying a predetermined first voltage and a variable second voltage, the device may be turned from an OFF state to an ON state.

4. The semiconductor device of claim 3 , wherein the semiconductor device is a n-type device configured such that when the first voltage is from 0 to 1.5V and when the second voltage is varied from a negative value to 0V, the device is OFF at the negative value and is turned ON at 0V.

5. The semiconductor device of claim 1 , wherein a gate length of the first gate stack and/or the second gate stack is from 2 nm to 30 nm.

6. The semiconductor device of claim 1 , wherein the distance is from 2 nm to 30 nm.

7. The semiconductor device of claim 1 , wherein the two-dimensional material layer comprises a group IV two-dimensional material or a group III-V two-dimensional material.

8. The semiconductor device of claim 1 , wherein the two-dimensional material layer comprises a group V two-dimensional material.

9. The semiconductor device of claim 1 , wherein the two-dimensional material layer comprises a transition metal dichalcogenide.

10. A method for operating a semiconductor device, comprising:
providing the semiconductor device of claim 1 ;
applying the first gate voltage to the first gate stack for inducing the discrete energy levels and the depleted density of states in the conduction band or in the valence band in the two-dimensional material layer underneath the first gate stack;
modulating the second gate voltage of the second gate stack for turning the device from OFF to ON; and
applying the source-to-drain voltage.

11. The method of claim 10 , wherein the first gate voltage is from 0V to 1.5V.

12. The method of claim 10 , wherein the first gate voltage is at least 1V.

13. The method of claim 10 , wherein the second gate voltage is changed from −1V to 0V, whereby the device is turned from OFF to ON.

Assignees

• Imec Vzw
• Univ Leuven Kath

Inventors

• Pourtois Geoffrey
• Lu Anh Khoa
• Huyghebaert Cedric

Classifications

• H01L29/78645

  Electricity · mapped topic

• H01L29/78681

  Electricity · mapped topic

• H01L29/66977 Primary

  Electricity · mapped topic

• H01L29/78684

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic