Integrated circuits with varying gate structures and fabrication methods
US-2015243658-A1 · Aug 27, 2015 · US
US9899491B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9899491-B2 |
| Application number | US-201615182620-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 15, 2016 |
| Priority date | May 16, 2016 |
| Publication date | Feb 20, 2018 |
| Grant date | Feb 20, 2018 |
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A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another on the substrate. The second gate structure includes the barrier layer, a portion of the first work function layer and the conductive layer stacked one over another on the substrate, wherein the portion of the first work function layer has a smaller thickness than a thickness of the first work function layer.
Opening claim text (preview).
What is claimed is: 1. A semiconductor device, comprising: a substrate; a first gate structure disposed on the substrate, wherein the first gate structure comprises a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another sequentially on the substrate; and a second gate structure disposed on the substrate, wherein the second gate structure comprises the barrier layer, the first work function layer and the conductive layer stacked one over another sequentially on the substrate, wherein a portion of the first work function layer in the first gate structure has a smaller thickness than a thickness of a portion of the first work function layer in the second gate structure, and the first gate structure is separated from the second gate structure, wherein the first work function layer and the second work function layer comprises different materials respectively, and the first work function layer directly contacts the second work function layer, wherein the first work function layer is made of tantalum nitride, and the second work function layer is made of titanium nitride, wherein the portion of the first work function layer in the second gate structure directly contacts the conductive layer in the second gate structure, and the second work function layer in the first gate structure is disposed between the first work function layer and the conductive layer in the first gate structure. 2. The semiconductor device of claim 1 , further comprising: a first spacer disposed on the substrate and surrounding the first gate structure and the second gate structure. 3. The semiconductor device of claim 1 , wherein the first work function layer in the first gate structure has a thickness in the range of from 5 angstroms to 7 angstroms when the thickness of the first work function layer in the second gate structure is 10 angstroms. 4. The semiconductor device of claim 1 , wherein the first work function layer and the second work function layer have different conductivity types respectively. 5. The semiconductor device of claim 1 , further comprising: a dielectric layer disposed on the substrate and comprising a gate trench, wherein the first gate structure and the second gate structure are both disposed in the gate trench.
the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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