Head resistance buffer

Patent metadata

Field	Value
Publication number	US-9899466-B2
Application number	US-201615335818-A
Country	US
Kind code	B2
Filing date	Oct 27, 2016
Priority date	Dec 18, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

An integrated circuit with first and second resistors comprised of resistor bodies, resistor heads, and resistor buffer regions wherein the resistor buffer regions are disposed between the resistor body and the resistor heads. The width of the first and second resistors is different. The length of the first and second resistor buffer regions is different. The total head resistance which is equal to the resistor head resistance plus the resistor buffer region is equal for both the first and second resistors. A method is described for forming an integrated circuit with first and second resistors comprised of resistor bodies, resistor heads, and resistor buffer regions disposed between the resistor body and the resistor head wherein the width of the first and second resistors is different, wherein the length of the resistor buffer regions of the first and second resistors is different, and wherein the total head resistance which is equal to the resistor head resistance plus the resistor buffer region is equal for both the first and second resistors. A method is described for calculating the length of a resistor buffer region as a function of resistor width so that the resistance of the resistor head plus the resistor buffer region remains the same as resistor body width changes.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a first resistor comprising:
a first resistor body with a first body width;
a first resistor buffer region at a first end of the first resistor body and a second resistor buffer region at a second end of the first resistor body, the first and second resistor buffer regions each having a first buffer length;
a first resistor head separated from the first resistor body by the first resistor buffer region and a second resistor head separated from the first resistor by the second resistor buffer region, the first and second resistor heads each having a head width and a head length;

a second resistor comprising:
a second resistor body with a second body width different from the first body width;
a third resistor buffer region at a first end of the second resistor body and a fourth resistor buffer region at a second end of the second resistor body, the third and fourth resistor buffer regions each having a second buffer length different from the first buffer length;
a third resistor head separated from the second resistor body by the third resistor buffer region and a fourth resistor head separated from the second resistor by the fourth resistor buffer region, the third and fourth resistor heads each having said head width and said head length;

wherein the resistance of the first resistor head plus the first buffer region is equal to the resistance of the third resistor head plus the third buffer region.

2. The integrated circuit of claim 1 , wherein:
a width of a first end of the first buffer region is equal to the first body width;
a width of a second end of the first buffer region is equal to the head width;
a width of a first end of the third buffer region is equal to the second body width; and
a width of the second end of the third buffer region is equal to the head width.

3. The integrated circuit of claim 1 , wherein the first and second resistors are well resistors.

4. The integrated circuit of claim 1 , wherein the first and second resistors are diffusion resistors.

5. The integrated circuit of claim 1 , wherein the first and second resistors are polysilicon resistors.

6. The integrated circuit of claim 1 , wherein the first and second resistors are metal resistors.

7. A method of fabricating an integrated circuit comprising:
forming a first resistor by:
forming a first resistor body with a first body width;
forming a first resistor buffer region at a first end of the first resistor body and a second resistor buffer region at a second end of the first resistor body, the first and second resistor buffer regions each having a first buffer length; and
forming a first resistor head separated from the first resistor body by the first resistor buffer region and a second resistor head separated from the first resistor by the second resistor buffer region, the first and second resistor heads each having a head width and a head length; and

forming a second resistor by:
forming a second resistor body with a second body width different from the first body width;
forming a third resistor buffer region at a first end of the second resistor body and a fourth resistor buffer region at a second end of the second resistor body, the third and fourth resistor buffer regions each having a second buffer length different from the first buffer length; and
forming a third resistor head separated from the second resistor body by the third resistor buffer region and a fourth resistor head separated from the second resistor by the fourth resistor buffer region, the third and fourth resistor heads each having said head width and said head length;

wherein the resistance of the first resistor head plus the first buffer region is equal to the resistance of the third resistor head plus the third buffer region.

8. The method of claim 7 , wherein said first resistor body, said first and second resistor buffer regions, said first and second resistor heads, said second resistor body, said third and fourth resistor buffer regions and said third and fourth resistor heads comprise polysilicon.

9. The method of claim 7 , wherein said first resistor body, said first and second resistor buffer regions, said first and second resistor heads, said second resistor body, said third and fourth resistor buffer regions and said third and fourth resistor heads comprise a same metal material.

10. The method of claim 7 , wherein said first resistor body, said first and second resistor buffer regions, said first and second resistor heads, said second resistor body, said third and fourth resistor buffer regions and said third and fourth resistor heads each comprise a doped region of a substrate.

Assignees

• Texas Instruments Deutschland
• Texas Instruments Inc

Inventors

• Muenz Josef

Classifications

• H01L27/0207

  Electricity · mapped topic

• H01L28/20 Primary

  Electricity · mapped topic

• H10D89/10

  Integrated device layouts · CPC title

• H10D1/00

  Resistors, capacitors or inductors · CPC title

• H10D1/47 Primary

  Resistors having no potential barriers · CPC title