GOA unit and method for producing the same, gate driver circuit

Patent metadata

Field	Value
Publication number	US-9899430-B2
Application number	US-201615089815-A
Country	US
Kind code	B2
Filing date	Apr 4, 2016
Priority date	Apr 29, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Embodiments of the present disclosure provide a GOA unit and a method for producing the same and a gate driver circuit, which are directed to a field of display technique. The GOA unit includes: a TFT module and a capacitor structure formed on a substrate. The TFT module includes a gate electrode, a source electrode and a drain electrode, and the capacitor structure includes a first electrode and a second electrode configured to form a first capacitor. The gate of the TFT module is located in a same layer as the first electrode of the capacitor structure, the source electrode and the drain electrode of the TFT module are located in a same layer as the second electrode of the capacitor structure, and the second electrode has a groove. Embodiments of the present application are used for a display apparatus.

First claim

What is claimed is:

1. A gate driver on array (GOA) unit comprising:
a TFT module and a capacitor structure formed on a substrate, wherein the TFT module comprises a gate electrode, a first portion of an insulation layer, a first portion of a semiconductor layer, a source electrode and a drain electrode, and the capacitor structure comprises a first electrode, a second portion of the insulation layer, a second portion of the semiconductor layer and a second electrode configured to form a first capacitor;
wherein the gate electrode of the TFT module is located in a same layer as the first electrode of the capacitor structure, the source electrode and the drain electrode of the TFT module are located in a same layer as the second electrode of the capacitor structure, and the second electrode has at least one through groove which extends from the top of the second electrode through the second portion of the semiconductor layer and exposes the second portion of the insulation layer;
wherein a surface of the second electrode away from the first electrode is formed with a protection layer and a third electrode in sequence, the protection layer is provided with a via hole therein, and the second electrode is electrically connected with the third electrode by the via hole.

2. The GOA unit according to claim 1 , wherein a plurality of channels are disposed between the source electrode and drain electrode, the second electrode has a plurality of the through grooves, and a distribution density of the plurality of through grooves is equivalent to that of channels of the TFT module.

3. The GOA unit according to claim 2 , wherein the plurality of through grooves are distributed evenly.

4. The GOA unit according to claim 2 , wherein a surface of the second electrode away from the first electrode is formed with a protection layer and a third electrode in sequence, the protection layer is provided with a via hole therein, and the second electrode is electrically connected with the third electrode by the via hole.

5. The GOA unit according to claim 3 , wherein a surface of the second electrode away from the first electrode is formed with a protection layer and a third electrode in sequence, the protection layer is provided with a via hole therein, and the second electrode is electrically connected with the third electrode by the via hole.

6. The GOA unit according to claim 1 , wherein the third electrode is made of ITO material.

7. The GOA unit according to claim 4 , wherein the third electrode is made of ITO material.

8. A gate driver circuit, comprising a plurality of the GOA units according to claim 1 .

9. The gate driver circuit according to claim 8 , wherein a plurality of channels are disposed between the source electrode and drain electrode, the second electrode has a plurality of the through grooves, and a distribution density of the plurality of through grooves is equivalent to that of channels of the TFT module.

10. The gate driver circuit according to claim 9 , wherein the plurality of through grooves are distributed evenly.

11. The gate driver circuit according to claim 8 , wherein a surface of the second electrode away from the first electrode is formed with a protection layer and a third electrode in sequence, and the protection layer is provided with a via hole therein, and the second electrode is electrically connected with the third electrode by the via hole.

12. The gate driver circuit according to claim 9 , wherein a surface of the second electrode away from the first electrode is formed with a protection layer and a third electrode in sequence, the protection layer is provided with a via hole therein, and the second electrode is electrically connected with the third electrode by the via hole.

13. The gate driver circuit according to claim 10 , wherein a surface of the second electrode away from the first electrode is formed with a protection layer and a third electrode in sequence, the protection layer is provided with a via hole therein, and the second electrode is electrically connected with the third electrode by the via hole.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Zhang Xiaoxiang
• Kuo Tsung Chieh
• Liu Zheng
• Zhang Zhichao
• Liu Mingxuan
• Chen Xi

Classifications

• H01L29/41733

  Electricity · mapped topic

• H01L27/1288

  Electricity · mapped topic

• H01L27/124

  Electricity · mapped topic

• H01L28/82

  Electricity · mapped topic

• H01L28/88

  Electricity · mapped topic