Nanowire floating gate transistor

Patent metadata

Field	Value
Publication number	US-9343142-B2
Application number	US-201213344517-A
Country	US
Kind code	B2
Filing date	Jan 5, 2012
Priority date	Jan 5, 2012
Publication date	May 17, 2016
Grant date	May 17, 2016

Abstract

A floating gate transistor, memory cell, and method of fabricating a device. The floating gate transistor includes one or more gated wires substantially cylindrical in form. The floating gate transistor includes a first gate dielectric layer at least partially covering the gated wires. The floating gate transistor further includes a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer. The floating gate transistor also includes a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer.

First claim

What is claimed is:

1. A floating gate transistor comprising:
at least one gated wire substantially cylindrical in form;
a first gate dielectric layer at least partially covering the at least one gated wire;
a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer; and
a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer;
wherein the gate crystals of the plurality of gate crystals are physically separate from each other, wherein the first gate dielectric surrounds the second gate dielectric and the gate crystals are positioned between the first gate dielectric layer and the second gate dielectric layer.

2. The floating gate transistor of claim 1 , wherein the plurality of gate crystals are electrically non-insulating.

3. The floating gate transistor of claim 1 , wherein the plurality of gate crystals is polysilicon.

4. The floating gate transistor of claim 1 , wherein the plurality of gate crystals is configured to store an electric charge in the absence of an applied electric field.

5. The floating gate transistor of claim 1 , further comprising:
a semiconductor layer carrying the at least one gated wire; and
an insulator layer below the semiconductor layer, the insulator layer having a recessed region below the at least one gated wire.

6. The floating gate transistor of claim 5 , wherein the recessed region is covered by the first gate dielectric layer.

7. The floating gate transistor of claim 5 , further comprising:
wherein the semiconductor layer includes a source pad and a drain pad; and
wherein the at least one gated wire is fabricated between the source pad and drain pad.

8. The floating gate transistor of claim 7 , further comprising:
a drain silicide layer above the drain pad; and
a source silicide layer above the source pad.

9. The floating gate transistor of claim 1 , further comprising:
a gate conductor layer electrically coupled to the second gate dielectric layer.

10. The floating gate transistor of claim 9 , further comprising:
a planarized dielectric layer; and
at least one gate sidewall spacer positioned between the planarized dielectric layer and the gate conductor layer.

11. The floating gate transistor of claim 1 , wherein the at least one gated wire is less than 20 nanometers in diameter.

12. The floating gate transistor of claim 1 , wherein the first gate dielectric layer is in physical contact with the at least one gated wire.

13. The floating gate transistor of claim 1 , wherein the gate crystals are positioned radially about the gated wire.

14. A memory cell comprising: at least one gated wire substantially cylindrical in form;
a first gate dielectric layer in physical contact with the at least one gated wire and at least partially covering the at least one gated wire;
a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer; and
a second gate dielectric layer covering the plurality of gate crystals and first gate dielectric layer; and
wherein the first gate dielectric layer surrounds the second gate dielectric layer and the gate crystals are positioned between the first gate dielectric layer and the second gate dielectric layer.

15. The memory cell of claim 14 , wherein the plurality of gate crystals is configured to store an electric charge in the absence of an applied electric field.

16. The memory cell of claim 14 , further comprising:
a semiconductor layer carrying the at least one gated wire; and
an insulator layer below the semiconductor layer, the insulator layer having a recessed region below the at least one gated wire, wherein the recessed region is covered by the first gate dielectric layer; and
a gate conductor layer enclosing the second gate dielectric layer.

17. The memory cell of claim 14 , wherein each of the at least one gated wire is less than 20 nanometers in diameter.

18. The memory cell of claim 14 , wherein gate crystals of the plurality of gate crystals are physically separate from each other.

19. The memory cell of claim 14 , wherein the gate crystals are positioned radially about the gated wire.

20. A floating gate transistor comprising:
at least one gated wire substantially cylindrical in form;
a first gate dielectric layer at least partially covering the at least one gated wire;
a plurality of gate crystals discontinuously arranged upon the first gate dielectric layer; and
a second gate dielectric layer covering the plurality of gate crystals and the first gate dielectric layer such that the plurality of gate crystals are positioned between and in physical contact with the first gate dielectric layer and the second gate dielectric layer;
wherein the gate crystals of the plurality of gate crystals are physically separate from each other; and
wherein the first gate dielectric layer surrounds the second gate dielectric layer and the gate crystals are positioned between the first gate dielectric layer and the second gate dielectric layer.

Assignees

• Bangsaruntip Sarunya
• Cohen Guy
• Majumdar Amlan
• Sleight Jeffrey W
• Globalfoundries Inc

Inventors

• Bangsaruntip Sarunya
• Cohen Guy
• Majumdar Amlan
• Sleight Jeffrey W

Classifications

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6894

  having one gate at least partly in a trench · CPC title

• H10D30/6893

  wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate · CPC title

• H10D30/681

  having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688) · CPC title