Wiring substrate and semiconductor device

Patent metadata

Field	Value
Publication number	US-9899304-B2
Application number	US-201615381916-A
Country	US
Kind code	B2
Filing date	Dec 16, 2016
Priority date	Dec 25, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

A wiring substrate includes a first wiring layer that is an uppermost wiring layer, a protective insulation layer that covers the first wiring layer, and a first through hole that extends through the protective insulation layer in a thickness-wise direction to partially expose an upper surface of the first wiring layer. The first through hole includes a recess defined in an upper surface of the protective insulation layer by a curved wall surface and an opening that extends from the upper surface of the first wiring layer to a bottom of the recess and is in communication with the recess. The opening is smaller than the recess in a plan view.

First claim

The invention claimed is:

1. A wiring substrate comprising:
a first wiring layer that is an uppermost wiring layer;
a protective insulation layer that covers the first wiring layer;
a first through hole that extends through the protective insulation layer in a thickness-wise direction to partially expose an upper surface of the first wiring layer, the first through hole including:
a recess defined in an upper surface of the protective insulation layer by a curved wall surface, and
an opening that extends from the upper surface of the first wiring layer to a bottom of the recess and is in communication with the recess, wherein the opening is smaller than the recess in a plan view;

a surface finish layer formed on the upper surface of the first wiring layer exposed by the opening; and
a solder bump bonded to the surface finish layer,
wherein an upper surface of the surface finish layer is located at a lower position than a corner that connects a lower end of the wall surface of the recess and an upper end of a wall surface of the opening, and
wherein an upper surface of the solder bump is located at a position that is higher than the corner and lower than the upper surface of the protective insulation layer.

2. The wiring substrate according to claim 1 , wherein the first through hole has the form of a stemmed bowl.

3. A semiconductor device comprising:
the wiring substrate according to claim 1 ; and
a semiconductor chip including a connection terminal bonded to the solder bump, wherein the semiconductor chip is flip-chip-mounted on the wiring substrate.

4. A wiring substrate comprising:
a first wiring layer that is an uppermost wiring layer;
a second wiring layer that is an uppermost wiring layer, wherein the first wiring layer and the second wiring layer are separated from each other on the same plane;
a protective insulation layer that covers the first wiring layer and the second wiring layer;
a first through hole that extends through the protective insulation layer in a thickness-wise direction to partially expose an upper surface of the first wiring layer; and
a second through hole that extends through the protective insulation layer in the thickness-wise direction to partially expose an upper surface of the second wiring layer, wherein
the first through hole includes
a recess defined in an upper surface of the protective insulation layer by a curved wall surface, and
an opening that extends from the upper surface of the first wiring layer to a bottom of the recess and is in communication with the recess, wherein the opening is smaller than the recess in a plan view,

the first through hole is defined by a wall surface that includes a step at an intermediate position in the thickness-wise direction, wherein the step defines the recess and the opening,
the second through hole is larger than the recess in a plan view, and
the second through hole is defined by a wall surface that is free of a step at an intermediate position in the thickness-wise direction.

5. The wiring substrate according to claim 4 , further comprising a surface finish layer formed on the upper surface of the first wiring layer exposed by the opening,
wherein an upper surface of the surface finish layer is located at a lower position than a corner that connects a lower end of the wall surface of the recess and an upper end of a wall surface of the opening.

6. The wiring substrate according to claim 5 , further comprising a solder bump bonded to the surface finish layer.

7. The wiring substrate according to claim 4 , further comprising a surface finish layer located on the upper surface of the first wiring layer exposed by the opening,
wherein an upper surface of the surface finish layer is located at a higher position than a corner that connects a lower end of the wall surface of the recess and an upper end of a wall surface of the opening.

8. The wiring substrate according to claim 7 , wherein the surface finish layer includes
a base portion with which the opening is filled, and
a distal portion located in a bottom of the recess, wherein the distal portion is larger than the base portion in a plan view.

9. The wiring substrate according to claim 7 , further comprising a solder bump bonded to the surface finish layer.

10. The wiring substrate according to claim 4 , wherein the first through hole has the form of a stemmed bowl.

11. A semiconductor device comprising:
the wiring substrate according to claim 6 ; and
a semiconductor chip including a connection terminal bonded to the solder bump, wherein the semiconductor chip is flip-chip-mounted on the wiring substrate.

12. A semiconductor device comprising:
the wiring substrate according to claim 9 ; and
a semiconductor chip including a connection terminal bonded to the solder bump, wherein the semiconductor chip is flip-chip-mounted on the wiring substrate.

Assignees

• Shinko Electric Ind Co

Inventors

• Imafuji Kei
• Yoshizawa Keiji
• Yoshino Hirokazu
• Uchiyama Kenta

Classifications

• H10W70/69

  Insulating materials thereof · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W90/701 Primary

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title