Thermal interface material layer and package-on-package device including the same

Patent metadata

Field	Value
Publication number	US-9899294-B2
Application number	US-201314910280-A
Country	US
Kind code	B2
Filing date	Aug 12, 2013
Priority date	Aug 12, 2013
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.

First claim

The invention claimed is:

1. A thermal interface material layer interposed between a lower semiconductor package and an upper semiconductor package, the thermal interface material layer having a modulus of elasticity of 500 kPa or less,
wherein the thermal interface material layer includes a resin layer and filler particles distributed in the resin layer, and
the resin layer has a modulus of elasticity of 500 kPA or less.

2. The thermal interface material layer of claim 1 , wherein the thermal interface material layer has Mohs hardness that is lower than 7.

3. The thermal interface material layer of claim 1 , wherein the thermal interface material layer has thermal conductivity of 1 W/mK or higher.

4. The thermal interface material layer of claim 1 , wherein the resin layer is formed of a silicon-based compound or a rubber-based compound.

5. The thermal interface material layer of claim 1 , wherein the filler particles have Mohs hardness that is lower than 7.

6. The thermal interface material layer of claim 5 , wherein the filler particles are configured to exhibit an insulation property.

7. The thermal interface material layer of claim 6 , wherein the filler particles are at least one of boron nitride particles and zinc oxide particles.

8. The thermal interface material layer of claim 6 , wherein at least one of the filler particles comprises a metal particle coated with an insulating layer, and the metal particle has Mohs hardness that is lower than 7.

9. The thermal interface material layer of claim 1 , wherein a content of the filler particles in the thermal interface material layer ranges from 60 wt % to 95 wt %.

10. The thermal interface material layer of claim 1 , wherein the thermal interface material layer has a Mohs hardness that is lower than 7.

11. The thermal interface material layer of claim 10 , wherein the thermal interface material layer has modulus of elasticity of 500 kPa or less.

12. The thermal interface material layer of claim 10 , wherein the thermal interface material layer has thermal conductivity of 1 W/mK or higher.

13. The thermal interface material layer of claim 10 , wherein
the filler particles have Mohs hardness that is lower than 7.

14. The thermal interface material layer of claim 13 , wherein the filler particles are configured to exhibit an insulation property.

15. The thermal interface material layer of claim 13 , wherein the filler particles are at least one of boron nitride particles and zinc oxide particles.

16. The thermal interface material layer of claim 13 , wherein at least one of the filler particles comprises a metal particle coated with an insulating layer, and the metal particle has Mohs hardness that is lower than 7.

17. The thermal interface material layer of claim 1 , wherein the resin layer is formed of a silicon-based compound or a rubber-based compound.

18. The thermal interface material layer of claim 13 , wherein a content of the filler particles in the thermal interface material layer ranges from 60 wt % to 95 wt %.

Assignees

• Na Min Ok
• Kim Jongkook
• Ryu Hyo Chang
• Park Jin Woo
• Son Bongjin
• Lee Jangwoo
• Samsung Electronics Co Ltd

Inventors

• Na Min Ok
• Kim Jongkook
• Ryu Hyo Chang
• Park Jin Woo
• Son Bongjin
• Lee Jangwoo

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title