Method for manufacturing array substrate, array substrate and mask

Patent metadata

Field	Value
Publication number	US-9899225-B2
Application number	US-201515105175-A
Country	US
Kind code	B2
Filing date	Sep 10, 2015
Priority date	May 18, 2015
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

An embodiment of present disclosure provides a method for manufacturing an array substrate, an array substrate manufactured by the method, and a mask. The method for manufacturing the array substrate includes: providing a mask including a transparent substrate, a light semi-transmission region, a light non-transmission region, and a light transmission region excluding the light semi-transmission region and the light non-transmission region being formed on the transparent substrate; forming a first mask pattern on a base substrate by means of the light non-transmission region of the mask; and forming a second mask pattern on the base substrate having the first mask pattern by means of the light semi-transmission region and the light non-transmission region of the mask.

First claim

What is claimed is:

1. A method for manufacturing an array substrate, wherein the method comprises:
providing a mask including a transparent substrate, a light semi-transmission region, a light non-transmission region, and a light transmission region excluding the light semi-transmission region and the light non-transmission region being formed on the transparent substrate, wherein the light semi-transmission region and the light non-transmission region have a same thickness as that of the transparent substrate and pass through the transparent substrate in a thickness direction, such that the transparent substrate has an uniform thickness as whole,
forming a first mask pattern on a base substrate by means of the light non-transmission region of the mask only; and
forming a second mask pattern on the base substrate having the first mask pattern by means of the light semi-transmission region and the light non-transmission region of the mask.

2. The method according to claim 1 , wherein, the step of forming the first mask pattern on the base substrate by means of the light non-transmission region of the mask comprises:
forming a first film layer on the base substrate having a source/drain electrode pattern of metal;
coating the first film layer formed on the base substrate with a negative photoresist;
aligning the light non-transmission region of the mask with the source/drain electrode pattern of metal, and exposing the base substrate coated with the negative photoresist to intensive light;
developing and etching the base substrate after exposure so as to obtain the first mask pattern; and
stripping off the negative photoresist.

3. The method according to claim 2 , wherein, the step of forming a second mask pattern on the base substrate having the first mask pattern by means of the light semi-transmission region and the light non-transmission region of the mask comprises:
forming a second film layer on the base substrate having the first mask pattern;
coating a positive photoresist on the second film layer formed on the base substrate;
aligning the light semi-transmission region and the light non-transmission region of the mask with an area around the source/drain electrode pattern of metal and the source/drain electrode pattern of metal, respectively, and exposing the base substrate coated with the positive photoresist to weak light;
developing and etching the base substrate after exposure so as to obtain the second mask pattern; and
stripping off the positive photoresist.

4. The method according to claim 1 , wherein, the first mask pattern is a via-hole pattern.

5. The method according to claim 2 , wherein, the first film layer is a passivation layer film.

6. The method according to claim 3 , wherein, the second film layer is an Indium-Tin Oxide film.

7. The method according to claim 1 , wherein, the light non-transmission region is located within the light semi-transmission region.

8. The method according to claim 1 , wherein, the shape of the light non-transmission region is chosen from any one of a rectangle, a square, a triangle and a circle.

9. The method according to claim 1 , wherein, the shape of the boundary of the light semi-transmission region is chosen from any one of a rectangle, a square, a triangle and a circle.

10. An array substrate, wherein, the array substrate is manufactured by the method according to claim 1 .

11. A mask, comprising: a transparent substrate, a light semi-transmission region, a light non-transmission region formed on the light semi-transmission region, and a light transmission region excluding the light semi-transmission region and the light non-transmission region being formed on the transparent substrate, wherein the light semi-transmission region and the light non-transmission region have a same thickness as that of the transparent substrate and pass through the transparent substrate in a thickness direction, such that the transparent substrate has an uniform thickness as whole;
wherein, only the light non-transmission region serves to form a first mask pattern of an array substrate, and the light semi-transmission region and the light non-transmission region serve to form a second mask pattern of the array substrate together.

12. The mask according to claim 11 , wherein, the mask further comprises a light semi-transmission film formed on the transparent substrate, and the light semi-transmission region is formed on the light semi-transmission film.

13. The mask according to claim 11 , wherein, the first mask pattern is a via-hole pattern.

14. The mask according to claim 11 , wherein, the shape of the light non-transmission region is chosen from any one of a rectangle, a square, a triangle and a circle.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co
• Beijing Boe Display Tech Co

Inventors

• Zhang Zhichao
• Kuo Tsung Chieh
• Liu Zheng
• Zhang Xiaoxiang
• Chen Xi
• Liu Mingxuan

Classifications

• H10D64/013 Primary

  of electrodes having a conductor capacitively coupled to a semiconductor by an insulator · CPC title

• H10D84/01 Primary

  Manufacture or treatment · CPC title

• H01L29/66742

  Electricity · mapped topic

• H01L27/1288

  Electricity · mapped topic

• G02F2001/136236

  Physics · mapped topic